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1. 发明申请

US20050118496A1 Method for regulating terminal voltage of cathode during overdischarge and cathode active material for lithium secondary battery 有权
标题翻译：用于调节过放电时阴极端电压的方法和锂二次电池正极活性材料
公开(公告)号：US20050118496A1
公开(公告)日：2005-06-02
申请号：US10950104
申请日：2004-09-24
申请人： Sung Chang , Seung Hong , Hyeong Kim , Duk Ryu , Eun Goh , Ho Lee , Jun Jeong , Jin Yeon , Hyung Lee
发明人： Sung Chang , Seung Hong , Hyeong Kim , Duk Ryu , Eun Goh , Ho Lee , Jun Jeong , Jin Yeon , Hyung Lee
IPC分类号： C01G53/04 , H01M4/131 , H01M4/50 , H01M4/505 , H01M4/52 , H01M4/525 , H01M10/0525 , H01M10/36 , H01M10/50
CPC分类号： H01M4/505 , H01M4/131 , H01M4/366 , H01M4/525 , H01M10/0525
摘要： Disclosed is a method for regulating terminal voltage of a cathode during overdischarge. Also disclosed is a lithium secondary battery, which is low in capacity loss after overdischarge, having excellent capacity restorability after overdischarge and shows an effect of preventing a battery from swelling at a high temperature.
摘要翻译：公开了一种用于在过放电期间调节阴极的端电压的方法。还公开了一种锂二次电池，其在过放电后的容量损失小，在过放电后具有优异的容量恢复性，并且显示出防止电池在高温下膨胀的效果。

2. 发明申请

US20070141475A1 Non-aqueous electrolyte and lithium secondary battery using the same 有权
标题翻译：非水电解质和锂二次电池使用相同
公开(公告)号：US20070141475A1
公开(公告)日：2007-06-21
申请号：US10588481
申请日：2004-02-10
申请人： Soon Ho Ahn , Jae Lee , Jeong Cho , Ho Lee , Mi Son , Hyeong Kim , Han Lee
发明人： Soon Ho Ahn , Jae Lee , Jeong Cho , Ho Lee , Mi Son , Hyeong Kim , Han Lee
IPC分类号： H01M10/40 , H01M4/58
CPC分类号： H01M10/052 , H01B1/122 , H01M10/0567 , H01M10/4235
摘要： The present invention relates to a nonaqueous electrolyte solution containing new additives and a lithium secondary battery including the same. More particularly, the invention relates to a nonaqueous electrolyte solution containing a lithium salt, an electrolyte compound, a first additive compound with an oxidation initiation potential of more than 4.2 V, and a second additive compound with an oxidation initiation potential of more than 4.2 V, which is higher in oxidation initiation potential than the first additive, and deposits oxidative products or form a polymer film, in oxidation, as well as a lithium secondary battery including the same. The present invention can provide a lithium secondary battery excellent in both the battery performance and the battery safety in overcharge by the combined use of the first additive and the second battery as additives to the nonaqueous electrolyte solution.
摘要翻译：本发明涉及含有新添加剂的非水电解液和包含该添加剂的锂二次电池。更具体地说，本发明涉及含有锂盐，电解质化合物，氧化起始电位大于4.2V的第一添加剂化合物和氧化起始电位大于4.2V的第二添加剂化合物的非水电解质溶液，其氧化起始电位高于第一添加剂，并且氧化产生氧化物或形成聚合物膜，以及包含其的锂二次电池。本发明可以通过将第一添加剂和第二电池作为添加剂与非水电解质溶液的组合使用，提供在电池性能和电池安全性方面优异的锂二次电池。

3. 发明申请

US20060263696A1 Additive for non-aqueous electrolyte and secondary battery using the same 有权
公开(公告)号：US20060263696A1
公开(公告)日：2006-11-23
申请号：US11406640
申请日：2006-04-19
申请人： Yu Kim , Hyeong Kim , Hye Cha , Ho Lee
发明人： Yu Kim , Hyeong Kim , Hye Cha , Ho Lee
IPC分类号： H01M10/40 , C07F9/02 , C07C25/13 , C07C211/00 , C07C319/00
CPC分类号： H01M10/0567 , H01M10/052 , H01M10/0569 , H01M10/4235
摘要： Disclosed is a compound represented by the following formula 1: wherein, each of R1˜R13 independently represents —H, —F, —Cl, —Br, —I, —OH, —SH, —COOH, —PO3H2, —NH2, —NO2, —O(CH2CH2O)nH (wherein, n is an integer of 1˜5), C1˜C12 alkyl group, C1˜C12 aminoalkyl group, C1˜C12 hydroxyalkyl group, C1˜C12 haloalkyl group, C2˜C12 alkenyl group, C1˜C12 alkoxy group, C1˜C12 alkylamino group, C1˜C12 dialkylamino group, C6˜C18 aryl group, C6˜C18 aminoaryl group, C6˜C18 hydroxyaryl group, C6˜C18 haloaryl group, C7˜C18 benzyl group, C7˜C18 aminobenzyl group, C7˜C18 hydroxybenzyl group, C7˜C18 halobenzyl group, or nitrile group (—CN); and at least one of R4˜R13 is nitrile group (—CN). A non-aqueous electrolyte comprising: (i) a lithium salt, (ii) a solvent, and (iii) a compound represented by formula 1; and a secondary battery comprising the non-aqueous electrolyte are also disclosed. When the compound represented by formula 1 is added to a non-aqueous electrolyte, it is possible to improve the safety of a secondary battery in an overcharged state.

4. 发明申请

US20080079086A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080079086A1
公开(公告)日：2008-04-03
申请号：US11831069
申请日：2007-07-31
申请人： Hyung-suk Jung , Jong-ho Lee , Sung-kee Han , Ho Lee , Ha-jin Lim
发明人： Hyung-suk Jung , Jong-ho Lee , Sung-kee Han , Ho Lee , Ha-jin Lim
IPC分类号： H01L21/336 , H01L27/085
CPC分类号： H01L21/823807
摘要： A semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device includes a semiconductor substrate in which PMOS transistor regions and NMOS transistor regions are formed, a PMOS transistor including P-type source and drain regions and a gate electrode, and an NMOS transistor formed on an Si channel region between N-type source and drain regions. The PMOS transistor is formed in each PMOS transistor region, and the gate electrode is formed on a high-dielectric gate insulating film formed on an SiGe channel region between the P-type source and drain regions. Further, the NMOS transistor includes a high-dielectric gate insulating film and a gate electrode formed on the gate insulating film, and the NMOS transistor is formed in each NMOS transistor region.
摘要翻译：一种半导体器件和半导体器件的制造方法，其中半导体器件包括其中形成有PMOS晶体管区域和NMOS晶体管区域的半导体衬底，包括P型源极和漏极区域的PMOS晶体管和栅极电极，以及形成在N型源区和漏区之间的Si沟道区上的NMOS晶体管。 PMOS晶体管形成在每个PMOS晶体管区域中，并且栅电极形成在形成在P型源区和漏区之间的SiGe沟道区上的高电介质栅极绝缘膜上。此外，NMOS晶体管包括高电介质栅极绝缘膜和形成在栅极绝缘膜上的栅电极，并且NMOS晶体管形成在每个NMOS晶体管区域中。

5. 发明授权

US08741710B2 Methods of fabricating semiconductor devices using a plasma process with non-silane gas including deuterium 有权
标题翻译：使用包括氘的非硅烷气体的等离子体处理制造半导体器件的方法
公开(公告)号：US08741710B2
公开(公告)日：2014-06-03
申请号：US12248431
申请日：2008-10-09
申请人： Dong-Suk Shin , Ho Lee , Tae-Gyun Kim
发明人： Dong-Suk Shin , Ho Lee , Tae-Gyun Kim
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/8238 , H01L21/28176 , H01L21/3003 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/8234 , H01L21/823475 , H01L21/823871 , H01L29/665
摘要： Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and forming a gate electrode on the gate oxide layer. An etch stop layer is formed on the gate oxide layer and the gate electrode. A plasma process is performed on the interface between the gate oxide layer and the substrate using a non-silane treatment gas including deuterium. An interlayer dielectric layer is formed on the etch stop layer. A bottom metal line is formed on the interlayer dielectric layer.
摘要翻译：使用包括氘的非硅烷气体的等离子体工艺制造半导体器件，并且其可以导致改进的器件可靠性和/或其他改进的器件操作特性。一种这样的方法可以包括在限定在衬底上的晶体管区域上形成栅极氧化层，并在栅极氧化物层上形成栅电极。在栅极氧化物层和栅电极上形成蚀刻停止层。使用包括氘的非硅烷处理气体在栅极氧化物层和衬底之间的界面上进行等离子体处理。在蚀刻停止层上形成层间电介质层。底层金属线形成在层间电介质层上。

6. 发明授权

US07682888B2 Methods of forming NMOS/PMOS transistors with source/drains including strained materials 有权
标题翻译：用包括应变材料在内的源极/漏极形成NMOS / PMOS晶体管的方法
公开(公告)号：US07682888B2
公开(公告)日：2010-03-23
申请号：US11435968
申请日：2006-05-17
申请人： Ho Lee , Tetsuji Ueno , Hwa-Sung Rhe
发明人： Ho Lee , Tetsuji Ueno , Hwa-Sung Rhe
IPC分类号： H01L21/4763
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02211 , H01L21/02293 , H01L21/3147 , H01L21/3148 , H01L21/3185 , H01L21/823814 , H01L29/045 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.
摘要翻译：形成集成电路的方法包括：在与其100°晶体取向平行的衬底上选择性地形成用于NMOS和PMOS晶体管的有源沟道区，并且选择性地形成具有碳（C）杂质的NMOS晶体管的源极/漏极区。

7. 发明授权

US07671420B2 Semiconductor devices having faceted channels and methods of fabricating such devices 有权
标题翻译：具有小平面通道的半导体器件和制造这种器件的方法
公开(公告)号：US07671420B2
公开(公告)日：2010-03-02
申请号：US11281599
申请日：2005-11-18
申请人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
发明人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
IPC分类号： H01L29/76 , H01L27/148 , H01L27/01
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L29/045 , H01L29/66795 , H01L29/7851 , H01L29/7853
摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.
摘要翻译：公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

8. 发明授权

US07611973B2 Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
标题翻译：在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法
公开(公告)号：US07611973B2
公开(公告)日：2009-11-03
申请号：US11154236
申请日：2005-06-16
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/28044 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/66628 , H01L29/66772
摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.
摘要翻译：在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶半导体图案，分别使用主半导体源气体和主蚀刻气体。使用选择性蚀刻气体去除非单晶外延半导体层。主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

9. 发明申请

US20090258463A1 METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY 有权
标题翻译：在半导体集成电路器件和半导体集成电路器件上制造不同厚度的硅 - 锗层的方法
公开(公告)号：US20090258463A1
公开(公告)日：2009-10-15
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/20 , H01L21/768
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

10. 发明申请

US20090224287A1 SEMICONDUCTOR DEVICE HAVING A LOCALLY BURIED INSULATION LAYER 审中-公开
标题翻译：具有局部绝缘绝缘层的半导体器件
公开(公告)号：US20090224287A1
公开(公告)日：2009-09-10
申请号：US12400408
申请日：2009-03-09
申请人： Dong-Suk Shin , Ho Lee , Myung-Sun Kim
发明人： Dong-Suk Shin , Ho Lee , Myung-Sun Kim
IPC分类号： H01L29/80
CPC分类号： H01L29/1083 , H01L21/76267 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device.
摘要翻译：提供了具有局部掩埋绝缘层的半导体器件及其制造方法，其中在基板上形成栅电极，并将氧离子注入有源区以形成局部掩埋的绝缘层。在局部掩埋的绝缘层上形成杂质层以形成源极/漏极。在源极/漏极和栅电极上形成硅化物层。局部埋入绝缘层可以防止结漏电，降低结电容，并防止MOS晶体管的临界电压由于体偏压而增加，从而改善器件的特性。

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