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1. 发明授权

US07671420B2 Semiconductor devices having faceted channels and methods of fabricating such devices 有权
标题翻译：具有小平面通道的半导体器件和制造这种器件的方法
公开(公告)号：US07671420B2
公开(公告)日：2010-03-02
申请号：US11281599
申请日：2005-11-18
申请人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
发明人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
IPC分类号： H01L29/76 , H01L27/148 , H01L27/01
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L29/045 , H01L29/66795 , H01L29/7851 , H01L29/7853
摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.
摘要翻译：公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

2. 发明授权

US07307274B2 Transistors having reinforcement layer patterns and methods of forming the same 有权
标题翻译：具有加强层图案的晶体管及其形成方法
公开(公告)号：US07307274B2
公开(公告)日：2007-12-11
申请号：US11204564
申请日：2005-08-15
申请人： Ho Lee , Dong-Suk Shin , Hwa-Sung Rhee , Ueno Tetsuji , Seung-Hwan Lee
发明人： Ho Lee , Dong-Suk Shin , Hwa-Sung Rhee , Ueno Tetsuji , Seung-Hwan Lee
IPC分类号： H01L29/06
CPC分类号： H01L29/66628 , H01L21/26586 , H01L29/1054 , H01L29/6659 , H01L29/66651 , H01L29/7834
摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.
摘要翻译：根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。最后，在半导体衬底的有源区上设置至少一个栅极图案。加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。每个加强层图案部分地暴露栅极图案的每个侧壁。杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

3. 发明申请

US20060148154A1 Semiconductor devices having faceted channels and methods of fabricating such devices 有权
标题翻译：具有小平面通道的半导体器件和制造这种器件的方法
公开(公告)号：US20060148154A1
公开(公告)日：2006-07-06
申请号：US11281599
申请日：2005-11-18
申请人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
发明人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L29/045 , H01L29/66795 , H01L29/7851 , H01L29/7853
摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.
摘要翻译：公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

4. 发明申请

US20080135879A1 METHOD OF FABRICATING CMOS TRANSISTOR AND CMOS TRANSISTOR FABRICATED THEREBY 失效
标题翻译：制造CMOS晶体管和CMOS晶体管的方法
公开(公告)号：US20080135879A1
公开(公告)日：2008-06-12
申请号：US12029884
申请日：2008-02-12
申请人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
发明人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
IPC分类号： H01L27/092
CPC分类号： H01L29/66636 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/165 , H01L29/4933 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.
摘要翻译：在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。同时，通过减少所需掩模的数量来简化制造过程。该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域大于第二导电型MOS晶体管的有源区中的第一深度。在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层凹陷区域。

5. 发明申请

US20060038200A1 Transistors having reinforcement layer patterns and methods of forming the same 有权
标题翻译：具有加强层图案的晶体管及其形成方法
公开(公告)号：US20060038200A1
公开(公告)日：2006-02-23
申请号：US11204564
申请日：2005-08-15
申请人： Ho Lee , Dong-Suk Shin , Hwa-Sung Rhee , Ueno Tetsuji , Seung-Hwan Lee
发明人： Ho Lee , Dong-Suk Shin , Hwa-Sung Rhee , Ueno Tetsuji , Seung-Hwan Lee
IPC分类号： H01L31/0328 , H01L21/336
CPC分类号： H01L29/66628 , H01L21/26586 , H01L29/1054 , H01L29/6659 , H01L29/66651 , H01L29/7834
摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.
摘要翻译：根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。最后，在半导体衬底的有源区上设置至少一个栅极图案。加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。每个加强层图案部分地暴露栅极图案的每个侧壁。杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

6. 发明授权

US07354835B2 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 有权
标题翻译：制造CMOS晶体管和CMOS晶体管的方法
公开(公告)号：US07354835B2
公开(公告)日：2008-04-08
申请号：US11157521
申请日：2005-06-21
申请人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
发明人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/165 , H01L29/4933 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.
摘要翻译：在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。同时，通过减少所需掩模的数量来简化制造过程。该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域大于第二导电类型MOS晶体管的有源区中的第一深度。在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层凹陷区域。

7. 发明申请

US20050280098A1 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 有权
标题翻译：制造CMOS晶体管和CMOS晶体管的方法
公开(公告)号：US20050280098A1
公开(公告)日：2005-12-22
申请号：US11157521
申请日：2005-06-21
申请人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
发明人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/76
CPC分类号： H01L29/66636 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/165 , H01L29/4933 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.
摘要翻译：在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。同时，通过减少所需掩模的数量来简化制造过程。该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域大于第二导电类型MOS晶体管的有源区中的第一深度。在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层凹陷区域。

8. 发明授权

US07611973B2 Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
标题翻译：在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法
公开(公告)号：US07611973B2
公开(公告)日：2009-11-03
申请号：US11154236
申请日：2005-06-16
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/28044 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/66628 , H01L29/66772
摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.
摘要翻译：在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶半导体图案，分别使用主半导体源气体和主蚀刻气体。使用选择性蚀刻气体去除非单晶外延半导体层。主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

9. 发明申请

US20060131656A1 CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
标题翻译：具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
公开(公告)号：US20060131656A1
公开(公告)日：2006-06-22
申请号：US11285978
申请日：2005-11-23
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/7834 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
摘要翻译：提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。第一和第二栅极图案分别设置成跨越第一和第二有源区域。第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。还提供了制造CMOS器件的方法。

10. 发明申请

US20060088968A1 Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
标题翻译：使用选择性外延生长技术制造半导体器件的方法
公开(公告)号：US20060088968A1
公开(公告)日：2006-04-27
申请号：US11299447
申请日：2005-12-08
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.
摘要翻译：使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。将具有凹部的基板装入反应室。将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

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