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1. 发明授权

US5933375A Main amplifier with fast output disablement 失效
标题翻译：主放大器具有快速输出禁用功能
公开(公告)号：US5933375A
公开(公告)日：1999-08-03
申请号：US932384
申请日：1997-09-17
申请人： Stephen Camacho , Robert M. Walker
发明人： Stephen Camacho , Robert M. Walker
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1051
摘要： An amplifier of a type having complementary output nodes in a data output mode of operation. When an external output enable signal is at a low level, the amplifier is enabled to output a data signal. When the output enable signal is set into a high level, the amplifier is brought into an output disable mode, in which both of its output nodes are set to a low level. The amplifier contains logic circuitry for supplying the output nodes with the data signal and output enable signal. In the output disable mode, a shunting circuit is arranged between the output nodes to provide two discharge paths for a charge stored at one of the output nodes when the signal at this output node transfers from a high level to a low level.
摘要翻译：一种在数据输出操作模式下具有互补输出节点的放大器。当外部输出使能信号处于低电平时，放大器使能输出数据信号。当输出使能信号被设置为高电平时，放大器进入输出禁止模式，其中两个输出节点都被设置为低电平。放大器包含用于向输出节点提供数据信号和输出使能信号的逻辑电路。在输出禁止模式中，当输出节点的信号从高电平转移到低电平时，在输出节点之间布置有分流电路以提供存储在输出节点之一处的电荷的两个放电路径。

2. 发明授权

US06279071B1 System and method for column access in random access memories 失效
标题翻译：随机存取存储器中的列访问的系统和方法
公开(公告)号：US06279071B1
公开(公告)日：2001-08-21
申请号：US09111277
申请日：1998-07-07
申请人： Robert M. Walker , Tim Lao , Stephen Camacho
发明人： Robert M. Walker , Tim Lao , Stephen Camacho
IPC分类号： G06F1200
CPC分类号： G11C7/1093 , G11C7/1018 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C8/10 , G11C11/4076 , G11C11/4087
摘要： A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.
摘要翻译：列访问系统具有列计数器，用于响应于外部地址产生列地址。列地址被锁存在解码列地址的地址解码器中，以选择DRAM中的列。命令解码器产生提供给地址解码器的列解码使能信号，以控制列地址的锁存，以及写入使能信号以及提供给写入驱动器的数据。在写入驱动器中提供数据锁存器用于锁存数据，直到均衡控制信号被激活。锁存的数据信号驱动全局输入/输出对，以向DRAM提供数据写入。

3. 发明授权

US6088760A Addressing system in a multi-port RAM having main and cache memories 失效
标题翻译：具有主和高速缓冲存储器的多端口RAM中的寻址系统
公开(公告)号：US6088760A
公开(公告)日：2000-07-11
申请号：US18343
申请日：1998-02-04
申请人： Robert M. Walker , Stephen Camacho , Rhonda Cassada
发明人： Robert M. Walker , Stephen Camacho , Rhonda Cassada
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G06F12/02 , G06F13/00
CPC分类号： G06F12/0893 , G11C11/005 , G11C7/1006
摘要： A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.
摘要翻译：具有通过全局总线耦合的DRAM主存储器和SRAM高速缓冲存储器的多端口存储器芯片。寻址系统使用户能够在DRAM和SRAM之间的数据传输同时执行外部数据端口和SRAM之间的数据传输。为了支持DRAM操作，存储器芯片上的DRAM地址引脚选择DRAM中的数据块，并且指示用于接收或传送数据的SRAM线。为了支持SRAM操作，SRAM地址引脚确定SRAM中的寻址行和字。为了减少存储器芯片上的引脚数量，DRAM地址引脚和SRAM地址引脚用于提供定义各种存储器操作的命令。

4. 发明授权

US6023187A Voltage pump for integrated circuit and operating method thereof 失效
标题翻译：集成电路用电压泵及其操作方法
公开(公告)号：US6023187A
公开(公告)日：2000-02-08
申请号：US997541
申请日：1997-12-23
申请人： Stephen Camacho , Robert Walker , Tim Lao
发明人： Stephen Camacho , Robert Walker , Tim Lao
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/073
摘要： One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.
摘要翻译：用于产生升压电压以驱动数据信号的装置的一个实施例包括电压泵，其包括耦合到输入信号的驱动器，用于从输入信号产生升压电压信号; 耦合到存储其电荷的数据信号的电容器; 以及当驱动信号被断言时向驱动器递送增量电荷的输出晶体管。因此，升压电压信号补偿驱动信号的逻辑电平的变化。在另一个实施例中，该装置还具有用于将多个数据信号组合成单个禁止低电平信号的门。禁止低电平信号耦合到输出晶体管。当所有数据信号都处于低逻辑电平时，禁止低电平信号关闭输出晶体管，禁止电路。结果，电路仅在需要时通过产生升压电压信号来节省功率。

5. 发明授权

US5933386A Driving memory bitlines using boosted voltage 失效
标题翻译：使用升压电压驱动内存位线
公开(公告)号：US5933386A
公开(公告)日：1999-08-03
申请号：US997509
申请日：1997-12-23
申请人： Robert Walker , Stephen Camacho , Tim Lao
发明人： Robert Walker , Stephen Camacho , Tim Lao
IPC分类号： G11C5/14 , G11C7/12 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22 , G11C5/145 , G11C7/12
摘要： An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.
摘要翻译：公开了一种用于驱动存储器阵列的位线驱动器的装置。存储器阵列具有行线，由位线驱动器驱动的互补的位线对，以及位线和行线的交点处的存储器单元。第一和第二互补写入数据线提供一些要写入驱动器和位的补码。升压电压的源极耦合到电平移位器，当写使能线和第一写数据线被断言时，电平转换器将升压电压传导到位线驱动器。当写使能线被断言时，数据位通过双稳态锁存器锁存到位线驱动器。驱动存储器阵列的位线的方法包括接收要写入位线的数据位和数据位的补码; 将一个数据位升高到大于存储器阵列的电源电压的电压; 并将数据位驱动到位线驱动器。

6. 发明授权

US06839288B1 Latch scheme with invalid command detector 有权
标题翻译：具有无效命令检测器的锁存方案
公开(公告)号：US06839288B1
公开(公告)日：2005-01-04
申请号：US10706146
申请日：2003-11-12
申请人： Jung Pill Kim , Jonghee Han , Stephen Camacho
发明人： Jung Pill Kim , Jonghee Han , Stephen Camacho
IPC分类号： G11C7/10 , G11C8/06 , G11C8/18 , G11C8/20 , G11C11/408 , G11C11/4093 , G11C7/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C11/4082 , G11C11/4093
摘要： Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced by preventing the outputs of the latch circuits from changing when an invalid command is detected. For some embodiments, an invalid command detector is provided that generates an invalid command signal used to inhibit latch circuits, in response to detecting an invalid command.
摘要翻译：提供了用于减少对锁存电路的输出的不必要的改变的方法和电路。当检测到无效命令时，可以通过防止锁存电路的输出改变来减少锁存电路的输出的不必要的改变。对于一些实施例，提供无效命令检测器，其响应于检测到无效命令而产生用于禁止锁存电路的无效命令信号。

7. 发明授权

US6167487A Multi-port RAM having functionally identical ports 失效
标题翻译：具有功能相同端口的多端口RAM
公开(公告)号：US6167487A
公开(公告)日：2000-12-26
申请号：US6190
申请日：1998-01-13
申请人： Stephen Camacho , Rhonda Cassada , William L. Randolph
发明人： Stephen Camacho , Rhonda Cassada , William L. Randolph
IPC分类号： G06F12/08 , G11C7/10 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/00 , G06F13/00
CPC分类号： G11C8/08 , G06F12/0893 , G11C7/1006 , G11C7/1018 , G11C7/1039 , G11C7/1072 , G11C7/1075 , G11C7/22 , G11C8/12 , G11C8/16 , G11C11/005
摘要： A memory having a SRAM, a DRAM, and two independent and functionally identical IO ports. Each port may be used as a read-only, a write-only, or a read-write port. One port may perform a read access to the SRAM, whereas the other port may carry out a write access to the SRAM in the same clock cycle. Each and every location of the SRAM may be accessed from any of the ports. Each port comprises a two-stage pipelined data path for providing a read or write access to the SRAM. Stage 1 decodes control and write enable signals, latches address signals and performs the output of read data. Stage 2 supports accesses to SRAM cells for writing and reading data. In a unified-port mode of operation, two 16-bit ports may be combined to produce a single port supporting a 32-bit write or read access to the SRAM. In a data burst mode of operation, each port may be programmed to select individual length of data bursts and individual burst type.
摘要翻译：具有SRAM，DRAM和两个独立且功能相同的IO端口的存储器。每个端口可以用作只读，只写或读写端口。一个端口可以执行对SRAM的读取访问，而另一个端口可以在相同的时钟周期中执行对SRAM的写访问。可以从任何端口访问SRAM的每个位置。每个端口包括用于提供对SRAM的读或写访问的两级流水线数据路径。阶段1解码控制和写入使能信号，锁存地址信号并执行读取数据的输出。阶段2支持对SRAM单元的访问，用于写入和读取数据。在统一端口操作模式下，可以组合两个16位端口，以产生支持对SRAM进行32位写入或读取访问的单个端口。在数据突发模式的操作中，每个端口可以被编程为选择数据突发和个别突发类型的单独长度。

8. 发明授权

US6101579A Multi-port memory device having masking registers 失效
标题翻译：具有掩蔽寄存器的多端口存储器件
公开(公告)号：US6101579A
公开(公告)日：2000-08-08
申请号：US6191
申请日：1998-01-13
申请人： William L. Randolph , Stephen Camacho , Rhonda Cassada
发明人： William L. Randolph , Stephen Camacho , Rhonda Cassada
IPC分类号： G06F12/08 , G11C7/10 , G11C8/16 , G11C11/00 , G06F13/00
CPC分类号： G06F12/0893 , G11C11/005 , G11C7/1006 , G11C8/16
摘要： A multi-port RAM (MPRAM) having a SRAM and a DRAM. A global bus is arranged between the DRAM and the SRAM to provide bi-directional transfer of 256-bit data blocks between the SRAM and the DRAM. Two independent input/output ports are coupled to the SRAM to enable a user to write or read data to or from the SRAM and DRAM. Byte masking is provided for each of the ports to mask bytes of data supplied to the MPRAM. A write-per-bit (WPB) mask register is arranged between the ports and the SRAM to prevent unnecessary bits of input data from being written into the SRAM. A byte write enable (BWE) mask register is arranged between the SRAM and the DRAM to prevent unnecessary bytes of data from being transferred from the SRAM to the DRAM. Each of the mask registers may be loaded with mask data from both of the ports concurrently, or from any one of them.
摘要翻译：具有SRAM和DRAM的多端口RAM（MPRAM）。在DRAM和SRAM之间布置全局总线，以在SRAM和DRAM之间提供256位数据块的双向传输。两个独立的输入/输出端口耦合到SRAM，以使用户能够向或从SRAM和DRAM写入或读取数据。为每个端口提供字节掩码以屏蔽提供给MPRAM的数据字节。在端口和SRAM之间布置了每位写入（WPB）掩码寄存器，以防止将不必要的输入数据位写入SRAM。在SRAM和DRAM之间布置一个字节写使能（BWE）掩码寄存器，以防止不必要的数据字节从SRAM传输到DRAM。每个掩码寄存器可以从两个端口同时或从其中的任何一个加载掩码数据。

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