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1. 发明授权

US6023187A Voltage pump for integrated circuit and operating method thereof 失效
标题翻译：集成电路用电压泵及其操作方法
公开(公告)号：US6023187A
公开(公告)日：2000-02-08
申请号：US997541
申请日：1997-12-23
申请人： Stephen Camacho , Robert Walker , Tim Lao
发明人： Stephen Camacho , Robert Walker , Tim Lao
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/073
摘要： One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.
摘要翻译：用于产生升压电压以驱动数据信号的装置的一个实施例包括电压泵，其包括耦合到输入信号的驱动器，用于从输入信号产生升压电压信号; 耦合到存储其电荷的数据信号的电容器; 以及当驱动信号被断言时向驱动器递送增量电荷的输出晶体管。因此，升压电压信号补偿驱动信号的逻辑电平的变化。在另一个实施例中，该装置还具有用于将多个数据信号组合成单个禁止低电平信号的门。禁止低电平信号耦合到输出晶体管。当所有数据信号都处于低逻辑电平时，禁止低电平信号关闭输出晶体管，禁止电路。结果，电路仅在需要时通过产生升压电压信号来节省功率。

2. 发明授权

US5933386A Driving memory bitlines using boosted voltage 失效
标题翻译：使用升压电压驱动内存位线
公开(公告)号：US5933386A
公开(公告)日：1999-08-03
申请号：US997509
申请日：1997-12-23
申请人： Robert Walker , Stephen Camacho , Tim Lao
发明人： Robert Walker , Stephen Camacho , Tim Lao
IPC分类号： G11C5/14 , G11C7/12 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22 , G11C5/145 , G11C7/12
摘要： An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.
摘要翻译：公开了一种用于驱动存储器阵列的位线驱动器的装置。存储器阵列具有行线，由位线驱动器驱动的互补的位线对，以及位线和行线的交点处的存储器单元。第一和第二互补写入数据线提供一些要写入驱动器和位的补码。升压电压的源极耦合到电平移位器，当写使能线和第一写数据线被断言时，电平转换器将升压电压传导到位线驱动器。当写使能线被断言时，数据位通过双稳态锁存器锁存到位线驱动器。驱动存储器阵列的位线的方法包括接收要写入位线的数据位和数据位的补码; 将一个数据位升高到大于存储器阵列的电源电压的电压; 并将数据位驱动到位线驱动器。

3. 发明授权

US06279071B1 System and method for column access in random access memories 失效
标题翻译：随机存取存储器中的列访问的系统和方法
公开(公告)号：US06279071B1
公开(公告)日：2001-08-21
申请号：US09111277
申请日：1998-07-07
申请人： Robert M. Walker , Tim Lao , Stephen Camacho
发明人： Robert M. Walker , Tim Lao , Stephen Camacho
IPC分类号： G06F1200
CPC分类号： G11C7/1093 , G11C7/1018 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C8/10 , G11C11/4076 , G11C11/4087
摘要： A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.
摘要翻译：列访问系统具有列计数器，用于响应于外部地址产生列地址。列地址被锁存在解码列地址的地址解码器中，以选择DRAM中的列。命令解码器产生提供给地址解码器的列解码使能信号，以控制列地址的锁存，以及写入使能信号以及提供给写入驱动器的数据。在写入驱动器中提供数据锁存器用于锁存数据，直到均衡控制信号被激活。锁存的数据信号驱动全局输入/输出对，以向DRAM提供数据写入。

4. 发明授权

US5784329A Latched DRAM write bus for quickly clearing DRAM array with minimum power usage 失效
标题翻译：锁存DRAM写入总线，以最小的功耗快速清除DRAM阵列
公开(公告)号：US5784329A
公开(公告)日：1998-07-21
申请号：US781388
申请日：1997-01-13
申请人： Dennis Blankenship , Tim Lao , Rhonda Cassada
发明人： Dennis Blankenship , Tim Lao , Rhonda Cassada
IPC分类号： G11C7/10 , G11C7/20 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/20 , G11C11/4096 , G11C7/1006
摘要： The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.
摘要翻译：在重复写入周期期间通过重复切换和DRAM总线预充电消耗的功率通过在重复数据写入期间将数据线锁存到DRAM阵列而减少，以避免在每次写入之前预充电线的必要性。当重复写入发生时，会重复写入模式，并在重复写入结束时清除。

5. 发明授权

US5959937A Dual clocking scheme in a multi-port RAM 失效
标题翻译：双时钟方案在多端口RAM中
公开(公告)号：US5959937A
公开(公告)日：1999-09-28
申请号：US24559
申请日：1998-02-17
申请人： William L. Randolph , Rhonda Cassada , Tim Lao
发明人： William L. Randolph , Rhonda Cassada , Tim Lao
IPC分类号： G06F12/08 , G11C7/10 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/00 , G11C8/00
CPC分类号： G06F12/0893 , G11C11/005 , G11C7/1006 , G11C7/1018 , G11C7/1072 , G11C7/1075 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16
摘要： A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.
摘要翻译：多端口存储器芯片设置有通过全局总线耦合的DRAM主存储器和SRAM高速缓存存储器。两个时钟引脚布置在芯片的相对两侧以提供外部时钟信号。在与时钟引脚相关的焊盘附近提供输入时钟缓冲器，以产生缓冲的时钟信号。布置在芯片上的时钟发生器使用缓冲的时钟信号来产生用于同步存储器操作的内部时钟信号。分配在存储器芯片上的四个本地时钟缓冲器被提供有缓冲的时钟信号，以产生用于同步数据引脚输出的数据的本地时钟信号。

6. 发明授权

US5798972A High-speed main amplifier with reduced access and output disable time periods 失效
标题翻译：具有减少访问和输出禁用时间段的高速主放大器
公开(公告)号：US5798972A
公开(公告)日：1998-08-25
申请号：US767135
申请日：1996-12-19
申请人： Tim Lao , Dennis Blankenship , Rhonda Cassada
发明人： Tim Lao , Dennis Blankenship , Rhonda Cassada
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1051
摘要： An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.
摘要翻译：提供输出缓冲器以输出从存储器阵列读出的数据。输出缓冲器由主放大器和输出驱动器组成。主放大器的输入锁存级连接到从存储器阵列读出数据的前置放大器的输出端。电平移位器耦合到输入锁存级，以驱动输出驱动器的晶体管对中的晶体管之一。驱动器级耦合到输入锁存级以驱动输出驱动器晶体管对中的另一晶体管。输出使能信号被提供给电平移位器和驱动器级以控制输出驱动器。当输出使能信号设置为第一逻辑电平时，输出驱动器将有效数据提供给外部设备。当输出使能信号处于第二逻辑电平时，输出驱动器的输出变为浮置高阻抗状态以禁止数据输出。

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