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1. 发明授权

US5946262A RAM having multiple ports sharing common memory locations 失效
标题翻译： RAM具有多个端口共享公共存储器位置
公开(公告)号：US5946262A
公开(公告)日：1999-08-31
申请号：US954628
申请日：1997-10-20
申请人： William L. Randolph , Rhonda Cassada
发明人： William L. Randolph , Rhonda Cassada
IPC分类号： G11C11/41 , G06F12/08 , G11C7/10 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/00 , G11C11/401 , G11C8/00
CPC分类号： G11C7/1006 , G06F12/0893 , G11C11/005 , G11C7/1018 , G11C7/1072 , G11C7/1075 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16
摘要： A memory having a SRAM, a DRAM and two external IO ports is provided. The SRAM has three IO ports for enabling the external IO ports and the DRAM to access each and every memory cell in the DRAM. Each SRAM cell is provided with two IO ports coupled to the external IO ports, and with an IO port for transferring data to and from the DRAM. The triple-port SRAM cell comprises three input data lines coupled to a latching circuit for writing data supplied from the external IO ports and the DRAM, and three output data lines coupled to the latching system for reading stored data to the external IO ports and the DRAM. Three write address lines and three read address lines provide addressing of the SRAM cell for data writing and reading operations performed by the external IO ports and the DRAM. Each SRAM cell may be read concurrently via all three ports to make the most current data stored in the SRAM accessible from any port at any time.
摘要翻译：提供具有SRAM，DRAM和两个外部IO端口的存储器。 SRAM具有三个IO端口，用于使外部IO端口和DRAM访问DRAM中的每个存储单元。每个SRAM单元提供两个IO端口，它们耦合到外部IO端口，并具有一个用于将数据传输到DRAM的IO端口。三端口SRAM单元包括耦合到用于写入从外部IO端口和DRAM提供的数据的锁存电路的三个输入数据线，以及耦合到锁存系统的三个输出数据线，用于将存储的数据读取到外部IO端口，并且 DRAM。三个写地址线和三个读地址线提供SRAM单元的寻址，用于由外部IO端口和DRAM执行的数据写入和读取操作。可以通过所有三个端口同时读取每个SRAM单元，以使存储在SRAM中的最新数据随时从任何端口访问。

2. 发明授权

US5784329A Latched DRAM write bus for quickly clearing DRAM array with minimum power usage 失效
标题翻译：锁存DRAM写入总线，以最小的功耗快速清除DRAM阵列
公开(公告)号：US5784329A
公开(公告)日：1998-07-21
申请号：US781388
申请日：1997-01-13
申请人： Dennis Blankenship , Tim Lao , Rhonda Cassada
发明人： Dennis Blankenship , Tim Lao , Rhonda Cassada
IPC分类号： G11C7/10 , G11C7/20 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/20 , G11C11/4096 , G11C7/1006
摘要： The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.
摘要翻译：在重复写入周期期间通过重复切换和DRAM总线预充电消耗的功率通过在重复数据写入期间将数据线锁存到DRAM阵列而减少，以避免在每次写入之前预充电线的必要性。当重复写入发生时，会重复写入模式，并在重复写入结束时清除。

3. 发明授权

US5798972A High-speed main amplifier with reduced access and output disable time periods 失效
标题翻译：具有减少访问和输出禁用时间段的高速主放大器
公开(公告)号：US5798972A
公开(公告)日：1998-08-25
申请号：US767135
申请日：1996-12-19
申请人： Tim Lao , Dennis Blankenship , Rhonda Cassada
发明人： Tim Lao , Dennis Blankenship , Rhonda Cassada
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1051
摘要： An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.
摘要翻译：提供输出缓冲器以输出从存储器阵列读出的数据。输出缓冲器由主放大器和输出驱动器组成。主放大器的输入锁存级连接到从存储器阵列读出数据的前置放大器的输出端。电平移位器耦合到输入锁存级，以驱动输出驱动器的晶体管对中的晶体管之一。驱动器级耦合到输入锁存级以驱动输出驱动器晶体管对中的另一晶体管。输出使能信号被提供给电平移位器和驱动器级以控制输出驱动器。当输出使能信号设置为第一逻辑电平时，输出驱动器将有效数据提供给外部设备。当输出使能信号处于第二逻辑电平时，输出驱动器的输出变为浮置高阻抗状态以禁止数据输出。

4. 发明授权

US6167487A Multi-port RAM having functionally identical ports 失效
标题翻译：具有功能相同端口的多端口RAM
公开(公告)号：US6167487A
公开(公告)日：2000-12-26
申请号：US6190
申请日：1998-01-13
申请人： Stephen Camacho , Rhonda Cassada , William L. Randolph
发明人： Stephen Camacho , Rhonda Cassada , William L. Randolph
IPC分类号： G06F12/08 , G11C7/10 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/00 , G06F13/00
CPC分类号： G11C8/08 , G06F12/0893 , G11C7/1006 , G11C7/1018 , G11C7/1039 , G11C7/1072 , G11C7/1075 , G11C7/22 , G11C8/12 , G11C8/16 , G11C11/005
摘要： A memory having a SRAM, a DRAM, and two independent and functionally identical IO ports. Each port may be used as a read-only, a write-only, or a read-write port. One port may perform a read access to the SRAM, whereas the other port may carry out a write access to the SRAM in the same clock cycle. Each and every location of the SRAM may be accessed from any of the ports. Each port comprises a two-stage pipelined data path for providing a read or write access to the SRAM. Stage 1 decodes control and write enable signals, latches address signals and performs the output of read data. Stage 2 supports accesses to SRAM cells for writing and reading data. In a unified-port mode of operation, two 16-bit ports may be combined to produce a single port supporting a 32-bit write or read access to the SRAM. In a data burst mode of operation, each port may be programmed to select individual length of data bursts and individual burst type.
摘要翻译：具有SRAM，DRAM和两个独立且功能相同的IO端口的存储器。每个端口可以用作只读，只写或读写端口。一个端口可以执行对SRAM的读取访问，而另一个端口可以在相同的时钟周期中执行对SRAM的写访问。可以从任何端口访问SRAM的每个位置。每个端口包括用于提供对SRAM的读或写访问的两级流水线数据路径。阶段1解码控制和写入使能信号，锁存地址信号并执行读取数据的输出。阶段2支持对SRAM单元的访问，用于写入和读取数据。在统一端口操作模式下，可以组合两个16位端口，以产生支持对SRAM进行32位写入或读取访问的单个端口。在数据突发模式的操作中，每个端口可以被编程为选择数据突发和个别突发类型的单独长度。

5. 发明授权

US6157990A Independent chip select for SRAM and DRAM in a multi-port RAM 失效
标题翻译：在多端口RAM中独立选择SRAM和DRAM
公开(公告)号：US6157990A
公开(公告)日：2000-12-05
申请号：US12460
申请日：1998-01-23
申请人： William L. Randolph , Dennis Blankenship , Rhonda Cassada
发明人： William L. Randolph , Dennis Blankenship , Rhonda Cassada
IPC分类号： G06F12/08 , G11C7/10 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/00 , G06F13/00
CPC分类号： G11C7/22 , G06F12/0893 , G11C11/005 , G11C7/1006 , G11C7/1018 , G11C7/1072 , G11C7/1075 , G11C8/08 , G11C8/12 , G11C8/16
摘要： A multi-port RAM (MPRAM) having a SRAM and a DRAM on a single chip. Separate pins are provided on the chip to supply independent chip select signals for the SRAM and the DRAM. When the SRAM chip select signal is at a high level, a clock generator is prevented from producing an internal clock signal for the SRAM. As a result, no SRAM operation is performed in response to a SRAM command. Similarly, when the DRAM chip select signal is high, a clock generator produces no internal clock signal for the DRAM. As a result, DRAM operations are prevented from being performed in response to DRAM commands.
摘要翻译：在单个芯片上具有SRAM和DRAM的多端口RAM（MPRAM）。在芯片上提供单独的引脚，为SRAM和DRAM提供独立的片选信号。当SRAM芯片选择信号处于高电平时，防止时钟发生器产生用于SRAM的内部时钟信号。结果，不响应于SRAM命令执行SRAM操作。类似地，当DRAM芯片选择信号为高时，时钟发生器不产生用于DRAM的内部时钟信号。结果，防止DRAM操作响应于DRAM命令被执行。

6. 发明授权

US6101579A Multi-port memory device having masking registers 失效
标题翻译：具有掩蔽寄存器的多端口存储器件
公开(公告)号：US6101579A
公开(公告)日：2000-08-08
申请号：US6191
申请日：1998-01-13
申请人： William L. Randolph , Stephen Camacho , Rhonda Cassada
发明人： William L. Randolph , Stephen Camacho , Rhonda Cassada
IPC分类号： G06F12/08 , G11C7/10 , G11C8/16 , G11C11/00 , G06F13/00
CPC分类号： G06F12/0893 , G11C11/005 , G11C7/1006 , G11C8/16
摘要： A multi-port RAM (MPRAM) having a SRAM and a DRAM. A global bus is arranged between the DRAM and the SRAM to provide bi-directional transfer of 256-bit data blocks between the SRAM and the DRAM. Two independent input/output ports are coupled to the SRAM to enable a user to write or read data to or from the SRAM and DRAM. Byte masking is provided for each of the ports to mask bytes of data supplied to the MPRAM. A write-per-bit (WPB) mask register is arranged between the ports and the SRAM to prevent unnecessary bits of input data from being written into the SRAM. A byte write enable (BWE) mask register is arranged between the SRAM and the DRAM to prevent unnecessary bytes of data from being transferred from the SRAM to the DRAM. Each of the mask registers may be loaded with mask data from both of the ports concurrently, or from any one of them.
摘要翻译：具有SRAM和DRAM的多端口RAM（MPRAM）。在DRAM和SRAM之间布置全局总线，以在SRAM和DRAM之间提供256位数据块的双向传输。两个独立的输入/输出端口耦合到SRAM，以使用户能够向或从SRAM和DRAM写入或读取数据。为每个端口提供字节掩码以屏蔽提供给MPRAM的数据字节。在端口和SRAM之间布置了每位写入（WPB）掩码寄存器，以防止将不必要的输入数据位写入SRAM。在SRAM和DRAM之间布置一个字节写使能（BWE）掩码寄存器，以防止不必要的数据字节从SRAM传输到DRAM。每个掩码寄存器可以从两个端口同时或从其中的任何一个加载掩码数据。

7. 发明授权

US6088760A Addressing system in a multi-port RAM having main and cache memories 失效
标题翻译：具有主和高速缓冲存储器的多端口RAM中的寻址系统
公开(公告)号：US6088760A
公开(公告)日：2000-07-11
申请号：US18343
申请日：1998-02-04
申请人： Robert M. Walker , Stephen Camacho , Rhonda Cassada
发明人： Robert M. Walker , Stephen Camacho , Rhonda Cassada
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G06F12/02 , G06F13/00
CPC分类号： G06F12/0893 , G11C11/005 , G11C7/1006
摘要： A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.
摘要翻译：具有通过全局总线耦合的DRAM主存储器和SRAM高速缓冲存储器的多端口存储器芯片。寻址系统使用户能够在DRAM和SRAM之间的数据传输同时执行外部数据端口和SRAM之间的数据传输。为了支持DRAM操作，存储器芯片上的DRAM地址引脚选择DRAM中的数据块，并且指示用于接收或传送数据的SRAM线。为了支持SRAM操作，SRAM地址引脚确定SRAM中的寻址行和字。为了减少存储器芯片上的引脚数量，DRAM地址引脚和SRAM地址引脚用于提供定义各种存储器操作的命令。

8. 发明授权

US5959937A Dual clocking scheme in a multi-port RAM 失效
标题翻译：双时钟方案在多端口RAM中
公开(公告)号：US5959937A
公开(公告)日：1999-09-28
申请号：US24559
申请日：1998-02-17
申请人： William L. Randolph , Rhonda Cassada , Tim Lao
发明人： William L. Randolph , Rhonda Cassada , Tim Lao
IPC分类号： G06F12/08 , G11C7/10 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/00 , G11C8/00
CPC分类号： G06F12/0893 , G11C11/005 , G11C7/1006 , G11C7/1018 , G11C7/1072 , G11C7/1075 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/16
摘要： A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.
摘要翻译：多端口存储器芯片设置有通过全局总线耦合的DRAM主存储器和SRAM高速缓存存储器。两个时钟引脚布置在芯片的相对两侧以提供外部时钟信号。在与时钟引脚相关的焊盘附近提供输入时钟缓冲器，以产生缓冲的时钟信号。布置在芯片上的时钟发生器使用缓冲的时钟信号来产生用于同步存储器操作的内部时钟信号。分配在存储器芯片上的四个本地时钟缓冲器被提供有缓冲的时钟信号，以产生用于同步数据引脚输出的数据的本地时钟信号。

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