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1. 发明授权

US06279071B1 System and method for column access in random access memories 失效
标题翻译：随机存取存储器中的列访问的系统和方法
公开(公告)号：US06279071B1
公开(公告)日：2001-08-21
申请号：US09111277
申请日：1998-07-07
申请人： Robert M. Walker , Tim Lao , Stephen Camacho
发明人： Robert M. Walker , Tim Lao , Stephen Camacho
IPC分类号： G06F1200
CPC分类号： G11C7/1093 , G11C7/1018 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C8/10 , G11C11/4076 , G11C11/4087
摘要： A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.
摘要翻译：列访问系统具有列计数器，用于响应于外部地址产生列地址。列地址被锁存在解码列地址的地址解码器中，以选择DRAM中的列。命令解码器产生提供给地址解码器的列解码使能信号，以控制列地址的锁存，以及写入使能信号以及提供给写入驱动器的数据。在写入驱动器中提供数据锁存器用于锁存数据，直到均衡控制信号被激活。锁存的数据信号驱动全局输入/输出对，以向DRAM提供数据写入。

2. 发明授权

US5933375A Main amplifier with fast output disablement 失效
标题翻译：主放大器具有快速输出禁用功能
公开(公告)号：US5933375A
公开(公告)日：1999-08-03
申请号：US932384
申请日：1997-09-17
申请人： Stephen Camacho , Robert M. Walker
发明人： Stephen Camacho , Robert M. Walker
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1051
摘要： An amplifier of a type having complementary output nodes in a data output mode of operation. When an external output enable signal is at a low level, the amplifier is enabled to output a data signal. When the output enable signal is set into a high level, the amplifier is brought into an output disable mode, in which both of its output nodes are set to a low level. The amplifier contains logic circuitry for supplying the output nodes with the data signal and output enable signal. In the output disable mode, a shunting circuit is arranged between the output nodes to provide two discharge paths for a charge stored at one of the output nodes when the signal at this output node transfers from a high level to a low level.
摘要翻译：一种在数据输出操作模式下具有互补输出节点的放大器。当外部输出使能信号处于低电平时，放大器使能输出数据信号。当输出使能信号被设置为高电平时，放大器进入输出禁止模式，其中两个输出节点都被设置为低电平。放大器包含用于向输出节点提供数据信号和输出使能信号的逻辑电路。在输出禁止模式中，当输出节点的信号从高电平转移到低电平时，在输出节点之间布置有分流电路以提供存储在输出节点之一处的电荷的两个放电路径。

3. 发明授权

US6088760A Addressing system in a multi-port RAM having main and cache memories 失效
标题翻译：具有主和高速缓冲存储器的多端口RAM中的寻址系统
公开(公告)号：US6088760A
公开(公告)日：2000-07-11
申请号：US18343
申请日：1998-02-04
申请人： Robert M. Walker , Stephen Camacho , Rhonda Cassada
发明人： Robert M. Walker , Stephen Camacho , Rhonda Cassada
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G06F12/02 , G06F13/00
CPC分类号： G06F12/0893 , G11C11/005 , G11C7/1006
摘要： A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.
摘要翻译：具有通过全局总线耦合的DRAM主存储器和SRAM高速缓冲存储器的多端口存储器芯片。寻址系统使用户能够在DRAM和SRAM之间的数据传输同时执行外部数据端口和SRAM之间的数据传输。为了支持DRAM操作，存储器芯片上的DRAM地址引脚选择DRAM中的数据块，并且指示用于接收或传送数据的SRAM线。为了支持SRAM操作，SRAM地址引脚确定SRAM中的寻址行和字。为了减少存储器芯片上的引脚数量，DRAM地址引脚和SRAM地址引脚用于提供定义各种存储器操作的命令。

4. 外观设计

USD650609S1 Lighted, skeletal helicopter table 有权
标题翻译：点燃，骨骼直升机桌
公开(公告)号：USD650609S1
公开(公告)日：2011-12-20
申请号：US29370528
申请日：2010-08-02
申请人： Robert M. Walker , Laura B. Walker
设计人： Robert M. Walker , Laura B. Walker

5. 发明申请

US20120057421A1 DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS 有权
标题翻译：设备和系统提供减少的互连数量
公开(公告)号：US20120057421A1
公开(公告)日：2012-03-08
申请号：US13279513
申请日：2011-10-24
申请人： Robert M. Walker
发明人： Robert M. Walker
IPC分类号： G11C7/12 , G11C8/00
CPC分类号： G11C5/066 , G11C8/00 , G11C8/06
摘要： Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.
摘要翻译：公开了用于减少存储器件的外部互连量的方法，装置和系统。一种这样的方法，装置和系统的实现包括通过地址总线输入要被激活的下一行存储器单元的地址的第一部分。要激活的下一行存储单元的地址的第一部分被嵌入与先前激活的存储单元行相关的命令中。随后根据也通过地址总线接收的下一行存储器单元的地址的同时接收的第二部分激活下一行存储器单元。地址信号的分配可以减小地址总线的宽度，因此可以减少所需的相应的外部互连的数量。

6. 发明授权

US06337454B1 Method and apparatus for destroying a medical instrument 失效
标题翻译：破坏医疗器械的方法和装置
公开(公告)号：US06337454B1
公开(公告)日：2002-01-08
申请号：US09101390
申请日：1998-07-15
申请人： Robert M. Walker
发明人： Robert M. Walker
IPC分类号： B23K1122
CPC分类号： A61M5/3278 , A61B2050/364 , A61M2005/3283
摘要： A method and apparatus for destroying the metallic portion of an elongate medical instrument, such as a hypodermic needle, by locating the instrument in the apparatus in a position where the tip of the instrument electrically engages a contact surface of a first and a second electrode. The electrodes each have an electrical contact surface disposed in opposition and separated by a gap from each other, and each electrode is in electrical contact with a power source. The electric potential between the electrodes is sufficient to induce electrical resistance burning of the tip of the instrument when an electrical current is passed through the tip between the electrodes. During operation of the apparatus, the instrument is progressively advanced longitudinally relative to the electrodes to progressively consumes the shaft of the medical instrument as the burning tip continuously advances from the start position to a finish position.
摘要翻译：一种用于通过将器械定位在仪器的尖端电接合第一和第二电极的接触表面的位置来破坏诸如皮下注射针的细长医疗器械的金属部分的方法和装置。电极各自具有彼此相对设置并且彼此间隔开的电接触表面，并且每个电极与电源电接触。当电流通过电极之间的尖端时，电极之间的电位足以引起器械尖端的电阻燃烧。在装置的操作期间，随着燃烧尖端从起始位置连续前进到最终位置，仪器相对于电极纵向前进，逐渐消耗医疗器械的轴。

7. 发明申请

US20130151741A1 MEMORY APPARATUSES, COMPUTER SYSTEMS AND METHODS FOR ORDERING MEMORY RESPONSES 有权
公开(公告)号：US20130151741A1
公开(公告)日：2013-06-13
申请号：US13324877
申请日：2011-12-13
申请人： Robert M. Walker
发明人： Robert M. Walker
IPC分类号： G06F13/00 , G06F13/36
CPC分类号： G06F13/1626 , G06F13/1668 , G06F13/18
摘要： Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order.

8. 发明申请

US20110093665A1 MEMORY HAVING INTERNAL PROCESSORS AND METHODS OF CONTROLLING MEMORY ACCESS 有权
标题翻译：具有内部处理器的内存和控制存储器访问的方法
公开(公告)号：US20110093665A1
公开(公告)日：2011-04-21
申请号：US12603393
申请日：2009-10-21
申请人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
发明人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.
摘要翻译：提供具有内部处理器的记忆和在这种存储器内的数据通信方法。一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。提取单元可以基于银行的可用性来执行命令。在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器来等待存储体可用。

9. 发明授权

US5288964A Electrical apparatus for destroying a medical instrument 失效
标题翻译：用于破坏医疗器械的电器
公开(公告)号：US5288964A
公开(公告)日：1994-02-22
申请号：US986740
申请日：1992-12-08
申请人： Robert M. Walker , Roger A. Kimmel, Jr.
发明人： Robert M. Walker , Roger A. Kimmel, Jr.
IPC分类号： A61M5/32 , F23K11/22
CPC分类号： A61M5/3278 , A61M2005/3283
摘要： An apparatus for destroying a medical instrument includes a housing having a wall member with an aperture disposed therein. A first electrical connector member is mounted adjacent the wall member of the housing for engaging a portion of a medical instrument inserted through the aperture in the wall member. A second electrical connector member is disposed within the housing for engaging an end portion of a medical instrument inserted through the aperture in the wall member. The first and second electrical connector members are provided to be selectively connected to a supply of electric current for destroying the medical instrument by transmitting current from the first electrical connector member to the second electrical connector member and through a medical instrument for melting the same. The second electrical connector member may be spring biased toward the aperture and pivotally mounted.
摘要翻译：一种用于破坏医疗器械的装置包括具有其中设置有孔的壁构件的壳体。第一电连接器构件邻近壳体的壁构件安装，用于接合插入穿过壁构件中的孔的医疗器械的一部分。第二电连接器构件设置在壳体内，用于接合通过壁构件中的孔插入的医疗器械的端部。第一和第二电连接器构件被设置成选择性地连接到用于通过将电流从第一电连接器构件传递到第二电连接器构件并且通过用于熔化医疗器械的医疗器械来破坏医疗器械的电流。第二电连接器构件可以被弹簧偏置朝向孔并枢转地安装。

10. 发明授权

US08719516B2 Memory having internal processors and methods of controlling memory access 有权
标题翻译：具有内部处理器的内存和控制内存访问的方法
公开(公告)号：US08719516B2
公开(公告)日：2014-05-06
申请号：US12603393
申请日：2009-10-21
申请人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
发明人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.
摘要翻译：提供具有内部处理器的记忆和在这种存储器内的数据通信方法。一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。提取单元可以基于银行的可用性来执行命令。在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器等待存储体可用。

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