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1. 发明授权

US08532243B2 Digital hold in a phase-locked loop 有权
标题翻译：数字保持在锁相环
公开(公告)号：US08532243B2
公开(公告)日：2013-09-10
申请号：US11673819
申请日：2007-02-12
申请人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
发明人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
IPC分类号： H03D3/24
CPC分类号： G06F1/04 , H03L7/146 , H03L7/148 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
摘要翻译：在单片集成电路中容易实现的一种技术包括一种方法，包括至少部分地基于指示PLL的反馈信号之间的相位差的数字控制值，在参考时钟信号存在期间产生输出时钟信号和参考时钟信号。所述方法包括在缺少参考时钟信号期间产生输出时钟信号，并且至少部分地基于平均数字控制字，该数字控制字指示在存在参考时数字控制值的采样数目的平均值时钟信号，在参考时钟信号不存在之前的采样数量延迟时间。从多个样本中选择样本数，并且从多个延迟周期中选择延迟周期。

2. 发明申请

US20080191762A1 DIGITAL HOLD IN A PHASE-LOCKED LOOP 有权
标题翻译：数字保持在相位锁定环
公开(公告)号：US20080191762A1
公开(公告)日：2008-08-14
申请号：US11673819
申请日：2007-02-12
申请人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
发明人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
IPC分类号： H03L7/06 , G06F1/04
CPC分类号： G06F1/04 , H03L7/146 , H03L7/148 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
摘要翻译：在单片集成电路中容易实现的一种技术包括一种方法，包括至少部分地基于指示PLL的反馈信号之间的相位差的数字控制值，在参考时钟信号存在期间产生输出时钟信号和参考时钟信号。所述方法包括在缺少参考时钟信号期间产生输出时钟信号，并且至少部分地基于平均数字控制字，该数字控制字指示在存在参考时数字控制值的采样数目的平均值时钟信号，在参考时钟信号不存在之前的采样数量延迟时间。从多个样本中选择样本数，并且从多个延迟周期中选择延迟周期。

3. 发明申请

US20080079501A1 TECHNIQUE FOR SWITCHING BETWEEN INPUT CLOCKS IN A PHASE-LOCKED LOOP 有权
标题翻译：用于在相位锁定环路中切换输入时钟的技术
公开(公告)号：US20080079501A1
公开(公告)日：2008-04-03
申请号：US11537082
申请日：2006-09-29
申请人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
发明人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.
摘要翻译：在单片集成电路中容易实现的技术在切换输入参考时钟信号时减少或消除相位毛刺。该技术组合了脉冲相位差信号和脉冲相位差补偿信号，以基本上衰减相位差信号的直流分量，并至少部分衰减相位差信号的谐波分量。脉冲相位差补偿信号基于输入参考时钟信号之间的相位差的指示符。

4. 发明授权

US07405628B2 Technique for switching between input clocks in a phase-locked loop 有权
标题翻译：用于在锁相环中输入时钟之间切换的技术
公开(公告)号：US07405628B2
公开(公告)日：2008-07-29
申请号：US11537082
申请日：2006-09-29
申请人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
发明人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.
摘要翻译：在单片集成电路中容易实现的技术在切换输入参考时钟信号时减少或消除相位毛刺。该技术组合了脉冲相位差信号和脉冲相位差补偿信号，以基本上衰减相位差信号的直流分量，并至少部分衰减相位差信号的谐波分量。脉冲相位差补偿信号基于输入参考时钟信号之间的相位差的指示符。

5. 发明授权

US07443250B2 Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics 有权
标题翻译：可编程锁相环响应所选择的带宽和选定的参考时钟信号频率来调整电路特性
公开(公告)号：US07443250B2
公开(公告)日：2008-10-28
申请号：US11560989
申请日：2006-11-17
申请人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
发明人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
IPC分类号： H03L7/08 , H03L7/087 , H03L7/18
CPC分类号： H03L7/18 , H03L7/087 , H03L7/093
摘要： A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.
摘要翻译：易于在单片集成电路中实施的技术包括基于参考时钟信号和可选配置参数产生输出时钟信号的锁相环（PLL）。一种方法包括至少部分地基于参考时钟信号的选定频率和选择的PLL带宽向PLL电路提供所选择的配置信息。该方法包括至少部分地基于参考时钟信号和所选择的配置信息，由PLL电路产生输出时钟信号。该方法包括在存储电路中存储对应于参考时钟信号的频率范围和PLL带宽范围的多组配置信息。根据选择的频率和所选择的带宽，从多组配置信息中访问所选择的配置信息。

6. 发明申请

US20080079510A1 PROGRAMMABLE PHASE-LOCKED LOOP RESPONSIVE TO A SELECTED BANDWIDTH AND A SELECTED REFERENCE CLOCK SIGNAL FREQUENCY TO ADJUST CIRCUIT CHARACTERISTICS 有权
标题翻译：响应于选择的带宽的可编程相位锁定环路和选择的参考时钟信号频率来调整电路特性
公开(公告)号：US20080079510A1
公开(公告)日：2008-04-03
申请号：US11560989
申请日：2006-11-17
申请人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
发明人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
IPC分类号： H03B5/12
CPC分类号： H03L7/18 , H03L7/087 , H03L7/093
摘要： A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.
摘要翻译：易于在单片集成电路中实施的技术包括基于参考时钟信号和可选配置参数产生输出时钟信号的锁相环（PLL）。一种方法包括至少部分地基于参考时钟信号的选定频率和选择的PLL带宽向PLL电路提供所选择的配置信息。该方法包括至少部分地基于参考时钟信号和所选择的配置信息，由PLL电路产生输出时钟信号。该方法包括在存储电路中存储对应于参考时钟信号的频率范围和PLL带宽范围的多组配置信息。根据选择的频率和所选择的带宽，从多组配置信息中访问所选择的配置信息。

7. 发明授权

US08242849B1 Compensation for crystal offset in PLL-based crystal oscillators 有权
标题翻译：基于PLL的晶体振荡器的晶体偏移补偿
公开(公告)号：US08242849B1
公开(公告)日：2012-08-14
申请号：US13076081
申请日：2011-03-30
申请人： Srisai R. Seethamraju , William J. Anker
发明人： Srisai R. Seethamraju , William J. Anker
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L1/00
摘要： A crystal offset value is stored in non-volatile memory in an oscillator device. The crystal offset value corresponds to a ratio between a rated frequency of an output of a crystal oscillator and a measured frequency of the output of the crystal oscillator. A rated divide value that corresponds to a selected frequency for an output of the oscillator device assumes the crystal oscillator operates at its rated or ideal frequency. Thus, the rated divide value corresponds to the rated frequency. The rated divide value is adjusted by the crystal offset value to generate an adjusted divide value and the adjusted divide value is used to generate an output signal of the oscillator device with the selected frequency.
摘要翻译：晶体偏移值存储在振荡器器件中的非易失性存储器中。晶体偏移值对应于晶体振荡器的输出的额定频率与晶体振荡器的输出的测量频率之间的比率。对应于振荡器设备输出的选定频率的额定分频值假定晶体振荡器工作在其额定或理想频率。因此，额定分频值对应于额定频率。额定分频值通过晶体偏移值进行调整，生成调整后的分频值，调整后的分频值用于产生具有选定频率的振荡器装置的输出信号。

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