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1. 发明申请

US20080079501A1 TECHNIQUE FOR SWITCHING BETWEEN INPUT CLOCKS IN A PHASE-LOCKED LOOP 有权
标题翻译：用于在相位锁定环路中切换输入时钟的技术
公开(公告)号：US20080079501A1
公开(公告)日：2008-04-03
申请号：US11537082
申请日：2006-09-29
申请人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
发明人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.
摘要翻译：在单片集成电路中容易实现的技术在切换输入参考时钟信号时减少或消除相位毛刺。该技术组合了脉冲相位差信号和脉冲相位差补偿信号，以基本上衰减相位差信号的直流分量，并至少部分衰减相位差信号的谐波分量。脉冲相位差补偿信号基于输入参考时钟信号之间的相位差的指示符。

2. 发明授权

US07405628B2 Technique for switching between input clocks in a phase-locked loop 有权
标题翻译：用于在锁相环中输入时钟之间切换的技术
公开(公告)号：US07405628B2
公开(公告)日：2008-07-29
申请号：US11537082
申请日：2006-09-29
申请人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
发明人： Ronald B. Hulfachor , Srisai R. Seethamraju , Shailesh Chitnis
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.
摘要翻译：在单片集成电路中容易实现的技术在切换输入参考时钟信号时减少或消除相位毛刺。该技术组合了脉冲相位差信号和脉冲相位差补偿信号，以基本上衰减相位差信号的直流分量，并至少部分衰减相位差信号的谐波分量。脉冲相位差补偿信号基于输入参考时钟信号之间的相位差的指示符。

3. 发明授权

US07443250B2 Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics 有权
标题翻译：可编程锁相环响应所选择的带宽和选定的参考时钟信号频率来调整电路特性
公开(公告)号：US07443250B2
公开(公告)日：2008-10-28
申请号：US11560989
申请日：2006-11-17
申请人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
发明人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
IPC分类号： H03L7/08 , H03L7/087 , H03L7/18
CPC分类号： H03L7/18 , H03L7/087 , H03L7/093
摘要： A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.
摘要翻译：易于在单片集成电路中实施的技术包括基于参考时钟信号和可选配置参数产生输出时钟信号的锁相环（PLL）。一种方法包括至少部分地基于参考时钟信号的选定频率和选择的PLL带宽向PLL电路提供所选择的配置信息。该方法包括至少部分地基于参考时钟信号和所选择的配置信息，由PLL电路产生输出时钟信号。该方法包括在存储电路中存储对应于参考时钟信号的频率范围和PLL带宽范围的多组配置信息。根据选择的频率和所选择的带宽，从多组配置信息中访问所选择的配置信息。

4. 发明申请

US20080079510A1 PROGRAMMABLE PHASE-LOCKED LOOP RESPONSIVE TO A SELECTED BANDWIDTH AND A SELECTED REFERENCE CLOCK SIGNAL FREQUENCY TO ADJUST CIRCUIT CHARACTERISTICS 有权
标题翻译：响应于选择的带宽的可编程相位锁定环路和选择的参考时钟信号频率来调整电路特性
公开(公告)号：US20080079510A1
公开(公告)日：2008-04-03
申请号：US11560989
申请日：2006-11-17
申请人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
发明人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
IPC分类号： H03B5/12
CPC分类号： H03L7/18 , H03L7/087 , H03L7/093
摘要： A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.
摘要翻译：易于在单片集成电路中实施的技术包括基于参考时钟信号和可选配置参数产生输出时钟信号的锁相环（PLL）。一种方法包括至少部分地基于参考时钟信号的选定频率和选择的PLL带宽向PLL电路提供所选择的配置信息。该方法包括至少部分地基于参考时钟信号和所选择的配置信息，由PLL电路产生输出时钟信号。该方法包括在存储电路中存储对应于参考时钟信号的频率范围和PLL带宽范围的多组配置信息。根据选择的频率和所选择的带宽，从多组配置信息中访问所选择的配置信息。

5. 发明授权

US07079369B2 Active power/ground ESD trigger 有权
公开(公告)号：US07079369B2
公开(公告)日：2006-07-18
申请号：US10207625
申请日：2002-07-29
申请人： Ronald B. Hulfachor , Jay R. Chapin
发明人： Ronald B. Hulfachor , Jay R. Chapin
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD protective triggering circuit for a triggering circuit for a solid state ESD protective device. The arrangement is to provide a controlled current to the protective device that triggers the device so that the device snaps-back and additionally the triggering device enables the parasitic transistor to participate in the draining of the ESD current. The triggering circuit also terminates the current to the protective device when the ESD voltage starts to fall. The triggering circuit can be used in any computer controlled electronics system.

6. 发明授权

US06927460B1 Method and structure for BiCMOS isolated NMOS transistor 有权
标题翻译： BiCMOS隔离NMOS晶体管的方法和结构
公开(公告)号：US06927460B1
公开(公告)日：2005-08-09
申请号：US10368253
申请日：2003-02-18
申请人： Steven M. Leibiger , Ronald B. Hulfachor , Michael Harley-Stead , Daniel J. Hahn
发明人： Steven M. Leibiger , Ronald B. Hulfachor , Michael Harley-Stead , Daniel J. Hahn
IPC分类号： H01L21/8234 , H01L21/8249 , H01L27/06 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/94
CPC分类号： H01L27/0623 , H01L21/823481 , H01L21/823493 , H01L21/8249
摘要： A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.
摘要翻译：使用标准BiCMOS处理步骤和技术制造隔离NMOS晶体管的结构和方法。相对于标准工艺流程，隔离NMOS器件不需要额外的掩模和处理步骤。示出了在P阱下面覆盖有掩埋p型层的覆盖掩埋N型层的P型衬底。 N型区域围绕并隔离同一晶片上的P阱与其他器件。在源极和漏极连接的p阱中形成N +区，并且在栅极，漏极和源极结构上形成多个或其它这样的电导体，以使NMOS器件工作。寄生双极晶体管由电路设计，电流路径和偏置来管理，以确保寄生双极晶体管不导通。

7. 发明授权

US06894553B2 Capacitively coupled current boost circuitry for integrated voltage regulator 有权
标题翻译：用于集成稳压器的电容耦合电流升压电路
公开(公告)号：US06894553B2
公开(公告)日：2005-05-17
申请号：US10208951
申请日：2002-07-31
申请人： Ronald B. Hulfachor , James J. McDonald, II.
发明人： Ronald B. Hulfachor , James J. McDonald, II.
IPC分类号： G05F1/56 , G05F1/40 , H02M3/24
CPC分类号： G05F1/56
摘要： A current boost circuit that supplies additional current to a voltage reference power rail. When the voltage reference power rail drops due to an excessive current demand from the load, the drop is sensed and a switch is activated supplying additional current to the voltage reference rail. A gain stage is capacitively coupled to the reference voltage and any drop is transferred through this capacitor to a gain stage that amplifies the drop. The amplified drop is capacitively coupled to a solid state switch that turns on connecting an additional current source to the reference voltage rail. The solid state switch is biased just below its turn on threshold.
摘要翻译：电流升压电路，为电压基准电源轨提供额外的电流。当电压基准电源轨由于来自负载的过大的电流需求而下降时，感测到下降并且激活开关，向电压基准轨提供额外的电流。增益级与参考电压电容耦合，并且任何液滴通过该电容传递到放大液滴的增益级。放大的电压降电容耦合到固态开关，固态开关将附加电流源连接到参考电压轨。固态开关偏压刚好低于其开启阈值。

8. 发明授权

US06855964B2 Triggering of an ESD NMOS through the use of an N-type buried layer 失效
标题翻译：通过使用N型掩埋层来触发ESD NMOS
公开(公告)号：US06855964B2
公开(公告)日：2005-02-15
申请号：US10280313
申请日：2002-10-25
申请人： Ronald B. Hulfachor
发明人： Ronald B. Hulfachor
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L23/62 , H01L27/02 , H01L27/06 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0277
摘要： An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each alternate N-type structure are electrically connected to each other, to the buried N-type structures, and to the output contact; while the other N-type structures are electrically connected to each other and the P-well and to ground. When a positive ESD event occurs, a depletion zone is created in the P-well between the N-type buried structures and the N-type structures thereby increasing the resistivity of the structure. Moreover, when a positive ESD event occurs, the lateral NPN transistors on either side of the center N-type structure break down and snap back. The resulting current travels through the area of increased resistivity and thereby creates a larger voltage along the P-well from the center N-type structure out toward the distal N-type structures. The combination of the increased resistivity and the higher voltage act in combination to lower the triggering voltage of the ESD structure.
摘要翻译：具有内置于P型阱中的奇数N型结构的ESD NMOS结构。埋置的N型结构位于N型结构之间。中心N型结构和每个交替的N型结构彼此电连接到埋入的N型结构和输出触点; 而其他N型结构彼此电连接，并且P阱和接地。当发生正的ESD事件时，在N型掩埋结构和N型结构之间的P阱中产生耗尽区，从而增加了结构的电阻率。此外，当发生正的ESD事件时，中心N型结构两侧的侧面NPN晶体管分解并回跳。所产生的电流穿过电阻率增加的区域，从而沿着P-阱从中心N型结构向远端N型结构产生更大的电压。增加的电阻率和较高电压的组合组合起来以降低ESD结构的触发电压。

9. 发明授权

US08476939B1 Switching power supply gate driver 有权
标题翻译：开关电源门极驱动器
公开(公告)号：US08476939B1
公开(公告)日：2013-07-02
申请号：US13173364
申请日：2011-06-30
申请人： Anthony B. Candage , Ronald B. Hulfachor
发明人： Anthony B. Candage , Ronald B. Hulfachor
IPC分类号： H03D3/00
CPC分类号： H03K17/122 , H03K17/164 , H03K2217/0063 , H03K2217/0072
摘要： One configuration of the present disclosure is directed to a switch driver circuit. The switch driver circuit can include an input to receive a control signal; an output to control a state of an switch in accordance with the control signal; and a set of parallel switches. The set of parallel switches in the switch driver circuit includes a P-type field effect transistor in parallel with an N-type field effect transistor. During operation, via variations in the control signal, the control signal selectively and electrically couples a voltage source signal to the output of the switch driver circuit to control the state of the switch.
摘要翻译：本公开的一种配置涉及开关驱动器电路。开关驱动器电路可以包括用于接收控制信号的输入端; 根据控制信号控制开关的状态的输出; 和一组并行开关。开关驱动器电路中的并联开关组包括与N型场效应晶体管并联的P型场效应晶体管。在操作期间，通过控制信号的变化，控制信号选择性地将电压源信号耦合到开关驱动电路的输出，以控制开关的状态。

10. 发明授权

US07030669B2 Circuit to linearize gain of a voltage controlled oscillator over wide frequency range 有权
标题翻译：电路在宽频率范围内线性化压控振荡器的增益
公开(公告)号：US07030669B2
公开(公告)日：2006-04-18
申请号：US10779891
申请日：2004-02-17
申请人： Ronald B. Hulfachor , James J. McDonald, II
发明人： Ronald B. Hulfachor , James J. McDonald, II
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03L7/0995
摘要： A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square law relationship between a control voltage and a resulting current. The current is ultimately used to charge the delay capacitor. The net effect is a linear relationship of the VCO frequency and an input control voltage. The range of the linear relationship is extended by using square law current sources to provide suitable currents that extend the linear range when other active devices are no longer supporting the square law relationship. In addition bipolar device are used to compensate for temperature and batch to batch processing effects of FET devices.
摘要翻译：示出了使用多个延迟级的压控振荡器电路，其中最后阶段环回到第一级。通过对一个或多个电容器充电来形成每一级延迟。该电路使用有源元件，显示出控制电压和所得电流之间的平方律关系。电流最终用于对延迟电容器充电。净效应是VCO频率和输入控制电压的线性关系。通过使用平方律电流源来提供线性关系的范围，以提供适当的电流，当其他有源器件不再支持平方律关系时，延伸线性范围。此外，双极性器件用于补偿FET器件的温度和批次处理效果。

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