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1. 发明授权

US08532243B2 Digital hold in a phase-locked loop 有权
标题翻译：数字保持在锁相环
公开(公告)号：US08532243B2
公开(公告)日：2013-09-10
申请号：US11673819
申请日：2007-02-12
申请人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
发明人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
IPC分类号： H03D3/24
CPC分类号： G06F1/04 , H03L7/146 , H03L7/148 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
摘要翻译：在单片集成电路中容易实现的一种技术包括一种方法，包括至少部分地基于指示PLL的反馈信号之间的相位差的数字控制值，在参考时钟信号存在期间产生输出时钟信号和参考时钟信号。所述方法包括在缺少参考时钟信号期间产生输出时钟信号，并且至少部分地基于平均数字控制字，该数字控制字指示在存在参考时数字控制值的采样数目的平均值时钟信号，在参考时钟信号不存在之前的采样数量延迟时间。从多个样本中选择样本数，并且从多个延迟周期中选择延迟周期。

2. 发明申请

US20080191762A1 DIGITAL HOLD IN A PHASE-LOCKED LOOP 有权
标题翻译：数字保持在相位锁定环
公开(公告)号：US20080191762A1
公开(公告)日：2008-08-14
申请号：US11673819
申请日：2007-02-12
申请人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
发明人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
IPC分类号： H03L7/06 , G06F1/04
CPC分类号： G06F1/04 , H03L7/146 , H03L7/148 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
摘要翻译：在单片集成电路中容易实现的一种技术包括一种方法，包括至少部分地基于指示PLL的反馈信号之间的相位差的数字控制值，在参考时钟信号存在期间产生输出时钟信号和参考时钟信号。所述方法包括在缺少参考时钟信号期间产生输出时钟信号，并且至少部分地基于平均数字控制字，该数字控制字指示在存在参考时数字控制值的采样数目的平均值时钟信号，在参考时钟信号不存在之前的采样数量延迟时间。从多个样本中选择样本数，并且从多个延迟周期中选择延迟周期。

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