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1. 发明授权

US08242849B1 Compensation for crystal offset in PLL-based crystal oscillators 有权
标题翻译：基于PLL的晶体振荡器的晶体偏移补偿
公开(公告)号：US08242849B1
公开(公告)日：2012-08-14
申请号：US13076081
申请日：2011-03-30
申请人： Srisai R. Seethamraju , William J. Anker
发明人： Srisai R. Seethamraju , William J. Anker
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L1/00
摘要： A crystal offset value is stored in non-volatile memory in an oscillator device. The crystal offset value corresponds to a ratio between a rated frequency of an output of a crystal oscillator and a measured frequency of the output of the crystal oscillator. A rated divide value that corresponds to a selected frequency for an output of the oscillator device assumes the crystal oscillator operates at its rated or ideal frequency. Thus, the rated divide value corresponds to the rated frequency. The rated divide value is adjusted by the crystal offset value to generate an adjusted divide value and the adjusted divide value is used to generate an output signal of the oscillator device with the selected frequency.
摘要翻译：晶体偏移值存储在振荡器器件中的非易失性存储器中。晶体偏移值对应于晶体振荡器的输出的额定频率与晶体振荡器的输出的测量频率之间的比率。对应于振荡器设备输出的选定频率的额定分频值假定晶体振荡器工作在其额定或理想频率。因此，额定分频值对应于额定频率。额定分频值通过晶体偏移值进行调整，生成调整后的分频值，调整后的分频值用于产生具有选定频率的振荡器装置的输出信号。

2. 发明授权

US07443250B2 Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics 有权
标题翻译：可编程锁相环响应所选择的带宽和选定的参考时钟信号频率来调整电路特性
公开(公告)号：US07443250B2
公开(公告)日：2008-10-28
申请号：US11560989
申请日：2006-11-17
申请人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
发明人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
IPC分类号： H03L7/08 , H03L7/087 , H03L7/18
CPC分类号： H03L7/18 , H03L7/087 , H03L7/093
摘要： A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.
摘要翻译：易于在单片集成电路中实施的技术包括基于参考时钟信号和可选配置参数产生输出时钟信号的锁相环（PLL）。一种方法包括至少部分地基于参考时钟信号的选定频率和选择的PLL带宽向PLL电路提供所选择的配置信息。该方法包括至少部分地基于参考时钟信号和所选择的配置信息，由PLL电路产生输出时钟信号。该方法包括在存储电路中存储对应于参考时钟信号的频率范围和PLL带宽范围的多组配置信息。根据选择的频率和所选择的带宽，从多组配置信息中访问所选择的配置信息。

3. 发明申请

US20080079510A1 PROGRAMMABLE PHASE-LOCKED LOOP RESPONSIVE TO A SELECTED BANDWIDTH AND A SELECTED REFERENCE CLOCK SIGNAL FREQUENCY TO ADJUST CIRCUIT CHARACTERISTICS 有权
标题翻译：响应于选择的带宽的可编程相位锁定环路和选择的参考时钟信号频率来调整电路特性
公开(公告)号：US20080079510A1
公开(公告)日：2008-04-03
申请号：US11560989
申请日：2006-11-17
申请人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
发明人： Srisai R. Seethamraju , Ronald B. Hulfachor , William J. Anker , Richard J. Juhn
IPC分类号： H03B5/12
CPC分类号： H03L7/18 , H03L7/087 , H03L7/093
摘要： A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.
摘要翻译：易于在单片集成电路中实施的技术包括基于参考时钟信号和可选配置参数产生输出时钟信号的锁相环（PLL）。一种方法包括至少部分地基于参考时钟信号的选定频率和选择的PLL带宽向PLL电路提供所选择的配置信息。该方法包括至少部分地基于参考时钟信号和所选择的配置信息，由PLL电路产生输出时钟信号。该方法包括在存储电路中存储对应于参考时钟信号的频率范围和PLL带宽范围的多组配置信息。根据选择的频率和所选择的带宽，从多组配置信息中访问所选择的配置信息。

4. 发明授权

US06888826B1 Pointer generator design that provides multiple outputs that can be synchronized to different clocks 有权
标题翻译：指针发生器设计，提供可以与不同时钟同步的多个输出
公开(公告)号：US06888826B1
公开(公告)日：2005-05-03
申请号：US09875758
申请日：2001-06-06
申请人： Gary D. Martin , William J. Anker
发明人： Gary D. Martin , William J. Anker
IPC分类号： H04J3/06 , H04L12/56 , H04L12/50 , H04Q11/00
CPC分类号： H04J3/0623 , Y10S370/907
摘要： A SONET multiplexed communications system that facilitates the sharing of processing resources while reducing overall system complexity. The SONET multiplexed communications system includes a single multi-output pointer generator clocked by a system clock and a plurality of clock domain transfer circuits having respective FIFO buffers for transferring SONET signals from the system clock domain to respective outgoing line clock domains. The multi-output pointer generator and the clock domain transfer circuits compensate for timing differences between the system clock and the respective outgoing line clocks by either skipping or overwriting FIFO buffer address locations corresponding to TOH byte positions in outgoing SONET frames. The TOH bytes corresponding to the skipped or overwritten TOH byte positions are subsequently re-generated by respective TOH insertion circuits before the outgoing SONET frames are passed through outgoing SONET lines.
摘要翻译：一种SONET复用通信系统，其有助于共享处理资源，同时降低整体系统的复杂度。 SONET多路复用通信系统包括由系统时钟定时的单个多输出指针发生器和具有各自的FIFO缓冲器的多个时钟域传送电路，用于将SONET信号从系统时钟域传送到相应的出线时钟域。多输出指针发生器和时钟域传送电路通过跳过或覆盖对应于输出SONET帧中的TOH字节位置的FIFO缓冲器地址位置来补偿系统时钟和相应输出线路时钟之间的时序差异。对应于跳过或覆盖的TOH字节位置的TOH字节随后在输出SONET帧通过输出SONET线路之前由相应的TOH插入电路重新生成。

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