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1. 发明授权

US08532243B2 Digital hold in a phase-locked loop 有权
标题翻译：数字保持在锁相环
公开(公告)号：US08532243B2
公开(公告)日：2013-09-10
申请号：US11673819
申请日：2007-02-12
申请人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
发明人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
IPC分类号： H03D3/24
CPC分类号： G06F1/04 , H03L7/146 , H03L7/148 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
摘要翻译：在单片集成电路中容易实现的一种技术包括一种方法，包括至少部分地基于指示PLL的反馈信号之间的相位差的数字控制值，在参考时钟信号存在期间产生输出时钟信号和参考时钟信号。所述方法包括在缺少参考时钟信号期间产生输出时钟信号，并且至少部分地基于平均数字控制字，该数字控制字指示在存在参考时数字控制值的采样数目的平均值时钟信号，在参考时钟信号不存在之前的采样数量延迟时间。从多个样本中选择样本数，并且从多个延迟周期中选择延迟周期。

2. 发明申请

US20080191762A1 DIGITAL HOLD IN A PHASE-LOCKED LOOP 有权
标题翻译：数字保持在相位锁定环
公开(公告)号：US20080191762A1
公开(公告)日：2008-08-14
申请号：US11673819
申请日：2007-02-12
申请人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
发明人： Srisai R. Seethamraju , Jerrell P. Hein , Kenneth Kin Wai Wong , Qicheng Yu
IPC分类号： H03L7/06 , G06F1/04
CPC分类号： G06F1/04 , H03L7/146 , H03L7/148 , H03L7/18
摘要： A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
摘要翻译：在单片集成电路中容易实现的一种技术包括一种方法，包括至少部分地基于指示PLL的反馈信号之间的相位差的数字控制值，在参考时钟信号存在期间产生输出时钟信号和参考时钟信号。所述方法包括在缺少参考时钟信号期间产生输出时钟信号，并且至少部分地基于平均数字控制字，该数字控制字指示在存在参考时数字控制值的采样数目的平均值时钟信号，在参考时钟信号不存在之前的采样数量延迟时间。从多个样本中选择样本数，并且从多个延迟周期中选择延迟周期。

3. 发明授权

US08207766B2 Method and apparatus for quantization noise reduction in fractional-N PLLs 有权
$Method and apparatus for quantization noise reduction in fractional-N PLLs$
标题翻译：分数N PLL中量化噪声降低的方法和装置
公开(公告)号：US08207766B2
公开(公告)日：2012-06-26
申请号：US12732029
申请日：2010-03-25
申请人： Qicheng Yu
发明人： Qicheng Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/089 , H03L7/1976
摘要： A first current source supplies a first charge amount responsive to a first pulse signal from the phase frequency detector and a second current source supplies a second charge amount according to a fixed value and a variable value. The variable value corresponds to a phase difference between a first feedback clock signal and a hypothesized feedback clock signal with reduced quantization noise. The first and second charge amounts are of opposite polarity. A single set of first and second current sources perform the functions of charge pump and noise reduction DAC.
摘要翻译：第一电流源响应于来自相位频率检测器的第一脉冲信号提供第一充电量，而第二电流源根据固定值和可变值提供第二充电量。可变值对应于第一反馈时钟信号和具有降低的量化噪声的假设的反馈时钟信号之间的相位差。第一和第二电荷量具有相反的极性。单组第一和第二电流源执行电荷泵和降噪DAC的功能。

4. 发明申请

US20110234272A1 METHOD AND APPARATUS FOR CHARGE PUMP LINEARIZATION IN FRACTIONAL-N PLLS 有权
标题翻译：方法和装置中的充气泵线性化在零件
公开(公告)号：US20110234272A1
公开(公告)日：2011-09-29
申请号：US12732024
申请日：2010-03-25
申请人： Qicheng Yu
发明人： Qicheng Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/089 , H03L7/0898
摘要： Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.
摘要翻译：高效的技术提高了分数N个PLL中电荷泵的线性度。形成多个VCO时钟周期的反馈时钟脉冲并将其提供给相位频率检测器（PFD）。由PFD产生的下降脉冲是固定的，以消除与上升和下降电流源不匹配相关联的非线性。当脉冲下降时，即反馈时钟脉冲下降时，上升脉冲下降。

5. 发明授权

US08179163B2 Method and apparatus for charge pump linearization in fractional-N PLLs 有权
$Method and apparatus for charge pump linearization in fractional-N PLLs$
标题翻译：分数N PLL中电荷泵线性化的方法和装置
公开(公告)号：US08179163B2
公开(公告)日：2012-05-15
申请号：US12732024
申请日：2010-03-25
申请人： Qicheng Yu
发明人： Qicheng Yu
IPC分类号： H03D13/00 , G01R25/00
CPC分类号： H03L7/1976 , H03L7/089 , H03L7/0898
摘要： Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.
摘要翻译：高效的技术提高了分数N个PLL中电荷泵的线性度。形成多个VCO时钟周期的反馈时钟脉冲并将其提供给相位频率检测器（PFD）。由PFD产生的下降脉冲是固定的，以消除与上升和下降电流源不匹配相关联的非线性。当脉冲下降时，即反馈时钟脉冲下降时，上升脉冲下降。

6. 发明授权

US06377198B1 Definition of physical level of a logic output by a logic input 有权
标题翻译：通过逻辑输入定义逻辑输出的物理电平
公开(公告)号：US06377198B1
公开(公告)日：2002-04-23
申请号：US09596156
申请日：2000-03-20
申请人： Jerome Johnston , Saibun Wong , Qicheng Yu , Douglas F. Pastorello
发明人： Jerome Johnston , Saibun Wong , Qicheng Yu , Douglas F. Pastorello
IPC分类号： H03M300
CPC分类号： H03K17/6872 , H03K17/693
摘要： The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level. In the preferred embodiment of the present invention, a chip select signal {overscore (CS)} is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V+supply voltage) or the low level logic signal voltage ({overscore (CS)}) to produce an output digital logic signal. In a further embodiment of the present invention, separate logic level signals INH and INL may be selectively switched by control logic to generate an output logic level signal independent of supply voltages V+ and V−.
摘要翻译：本发明提供了一种通过将输出通过传输门连接到输入引脚来定义和维持这种物理水平的方法和装置。对于输出的某一状态，可以将一个输入电平馈送到输出以产生输出电压电平。在本发明的优选实施例中，使用芯片选择信号{overscore（CS）}来定义低电平逻辑信号。控制逻辑选择性地切换高电平逻辑信号电压（例如，V +电源电压）或低电平逻辑信号电压（{overscore（CS）}）以产生输出数字逻辑信号。在本发明的另一个实施例中，分离的逻辑电平信号INH和INL可以被控制逻辑选择性地切换以产生独立于电源电压V +和V-的输出逻辑电平信号。

7. 发明授权

US09699534B1 Time-domain multiplexed signal processing block and method for use with multiple MEMS devices 有权
公开(公告)号：US09699534B1
公开(公告)日：2017-07-04
申请号：US14487827
申请日：2014-09-16
申请人： Saroj Rout , Akhil K. Garlapati , Qicheng Yu
发明人： Saroj Rout , Akhil K. Garlapati , Qicheng Yu
IPC分类号： H04Q11/04 , G01C19/56 , H04J3/02 , G01C19/5776 , G01C19/5726
CPC分类号： H04Q11/0421 , G01C19/5726 , G01C19/5776 , G01P15/18 , H04J3/02 , H04Q9/00 , H04Q11/04 , H04Q2213/13213 , H04Q2213/13292
摘要： A sense channel signal processing block is time-domain multiplexed among multiple MEMS devices and utilizes an anti-aliasing filter disposed after track-and-hold switches, to prevent the bandwidth of the sense channel from being limited by the anti-aliasing filter.

8. 发明申请

US20110234269A1 METHOD AND APPARATUS FOR QUANTIZATION NOISE REDUCTION IN FRACTIONAL-N PLLS 有权
标题翻译：用于定量噪声减少的方法和装置
公开(公告)号：US20110234269A1
公开(公告)日：2011-09-29
申请号：US12732029
申请日：2010-03-25
申请人： Qicheng Yu
发明人： Qicheng Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/089 , H03L7/1976
摘要： A first current source supplies a first charge amount responsive to a first pulse signal from the phase frequency detector and a second current source supplies a second charge amount according to a fixed value and a variable value. The variable value corresponds to a phase difference between a first feedback clock signal and a hypothesized feedback clock signal with reduced quantization noise. The first and second charge amounts are of opposite polarity. A single set of first and second current sources perform the functions of charge pump and noise reduction DAC.
摘要翻译：第一电流源响应于来自相位频率检测器的第一脉冲信号提供第一充电量，而第二电流源根据固定值和可变值提供第二充电量。可变值对应于第一反馈时钟信号和具有降低的量化噪声的假设的反馈时钟信号之间的相位差。第一和第二电荷量具有相反的极性。单组第一和第二电流源执行电荷泵和降噪DAC的功能。

9. 发明授权

US06445330B1 Capacitively coupled references for isolated analog-to-digital converter systems 有权
标题翻译：用于隔离的模拟 - 数字转换器系统的电容耦合参考
公开(公告)号：US06445330B1
公开(公告)日：2002-09-03
申请号：US09834630
申请日：2001-04-16
申请人： Axel Thomsen , Qicheng Yu
发明人： Axel Thomsen , Qicheng Yu
IPC分类号： H03M112
CPC分类号： H03M1/0827 , H03M1/12
摘要： The present invention provides an alternative to Prior Art isolation techniques by providing a capacitively coupled reference voltage and a capacitively coupled gain calibration. The isolation technique of the present invention is based upon the idea of a near unity gain capacitive divider. If the load or parasitic capacitance is Cload and the isolation capacitance is Ciso, then the gain between input and output can be calculated as Vout/Vin=(Ciso)/(Ciso+Cload), which will be nearly unity (i.e., 1) when Ciso>>Cload. In addition, if Ciso>>Cload, the gain will also be largely insensitive to variations in Ciso and Cload. For example, if Cin is 100 ppm of Ciso, then a 10% variation in Ciso or Cload results in only a 10 ppm variation in the voltage gain.
摘要翻译：本发明通过提供电容耦合参考电压和电容耦合增益校准来提供现有技术隔离技术的替代方案。本发明的隔离技术基于近单位增益电容分压器的思想。如果负载或寄生电容为C负载，隔离电容为Ciso，则输入和输出之间的增益可以计算为Vout / Vin =（Ciso）/（Ciso + Cload），这将几乎是一致的（即1）当Ciso >> Cload。另外，如果Ciso >> Cload，增益也将在很大程度上不敏感于Ciso和Cload的变化。例如，如果Cin是Ciso的100ppm，则Ciso或Cload的10％变化导致电压增益只有10ppm的变化。

10. 发明授权

US6002355A Synchronously pumped substrate analog-to-digital converter (ADC) system and methods 失效
标题翻译：同步泵浦基板模数转换器（ADC）系统和方法
公开(公告)号：US6002355A
公开(公告)日：1999-12-14
申请号：US883364
申请日：1997-06-26
申请人： Bruce Del Signore , Qicheng Yu , Jerome E. Johnston
发明人： Bruce Del Signore , Qicheng Yu , Jerome E. Johnston
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/12
摘要： An analog-to-digital converter (ADC) architecture is fabricated on a semiconductor substrate which is negatively capacitively charge pumped below ground and subject to feedback regulation, rate measurements and adjustments. The ADC receives signal inputs of positive and negative polarity relative to ground, while being powered at 0V and 5V, without any negative power source input, as a result of a closed feedback loop which keeps the negative bias voltage constant as external supplies and component voltages vary. The high frequency pumping of the silicon substrate is subject to timing requirements which permit high resolution analog input signals to be converted in the presence of pump noise.
摘要翻译：在半导体衬底上制造模数转换器（ADC）架构，其负电容性电荷泵送在地下，并进行反馈调节，速率测量和调整。由于封闭的反馈环路使得负偏置电压恒定，因此外部电源和分量电压不变，ADC接收到相对于地的正极性和负极性的信号输入，同时在0V和5V电源下没有任何负电源输入变化。硅衬底的高频泵浦受到时序要求的限制，允许在存在泵浦噪声的情况下转换高分辨率模拟输入信号。

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