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1. 发明授权

US09699534B1 Time-domain multiplexed signal processing block and method for use with multiple MEMS devices 有权
公开(公告)号：US09699534B1
公开(公告)日：2017-07-04
申请号：US14487827
申请日：2014-09-16
申请人： Saroj Rout , Akhil K. Garlapati , Qicheng Yu
发明人： Saroj Rout , Akhil K. Garlapati , Qicheng Yu
IPC分类号： H04Q11/04 , G01C19/56 , H04J3/02 , G01C19/5776 , G01C19/5726
CPC分类号： H04Q11/0421 , G01C19/5726 , G01C19/5776 , G01P15/18 , H04J3/02 , H04Q9/00 , H04Q11/04 , H04Q2213/13213 , H04Q2213/13292
摘要： A sense channel signal processing block is time-domain multiplexed among multiple MEMS devices and utilizes an anti-aliasing filter disposed after track-and-hold switches, to prevent the bandwidth of the sense channel from being limited by the anti-aliasing filter.

2. 发明授权

US07405601B2 High-speed divider with pulse-width control 有权
标题翻译：高速分频器具有脉冲宽度控制
公开(公告)号：US07405601B2
公开(公告)日：2008-07-29
申请号：US11680026
申请日：2007-02-28
申请人： Akhil K. Garlapati , Lizhong Sun , Douglas F. Pastorello , Richard J. Juhn , Axel Thomsen
发明人： Akhil K. Garlapati , Lizhong Sun , Douglas F. Pastorello , Richard J. Juhn , Axel Thomsen
IPC分类号： H03K21/00
CPC分类号： H03K23/66 , H03K21/10 , H03L7/0805 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/193 , H03L7/1974 , H03L7/1976
摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.
摘要翻译：在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号。第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。

3. 发明授权

US07321225B2 Voltage reference generator circuit using low-beta effect of a CMOS bipolar transistor 有权
标题翻译：使用CMOS双极晶体管的低β效应的参考电压源电路
公开(公告)号：US07321225B2
公开(公告)日：2008-01-22
申请号：US10813837
申请日：2004-03-31
申请人： Akhil K. Garlapati , Bruce P. Del Signore , David Pietruszynski
发明人： Akhil K. Garlapati , Bruce P. Del Signore , David Pietruszynski
IPC分类号： G05F3/16
CPC分类号： G05F3/30 , G05F3/267
摘要： A voltage reference generator has been discovered that generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a cascaded current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has improved noise performance as compared to traditional bandgap circuits. These advantages are achieved by leveraging the low-beta effect of a CMOS bipolar transistor to generate a current proportional to an absolute temperature.
摘要翻译：已经发现了一种电压参考发生器，其产生小于2V的电源电压的硅的带隙电压的稳定参考电压，但是为级联电流镜提供足够的电压余量。在一个实施例中，与传统的带隙电路相比，电压参考发生器具有至少60dB的电源抑制比并且具有改善的噪声性能。这些优点通过利用CMOS双极晶体管的低β效应产生与绝对温度成比例的电流来实现。

4. 发明授权

US09343961B1 Ultrahigh voltage charge pump apparatus implemented with low voltage technology 有权
标题翻译：超高压电荷泵设备采用低压技术实现
公开(公告)号：US09343961B1
公开(公告)日：2016-05-17
申请号：US14486571
申请日：2014-09-15
申请人： Ronald J. Lipka , Akhil K. Garlapati
发明人： Ronald J. Lipka , Akhil K. Garlapati
IPC分类号： G05F1/10 , H02M3/07
CPC分类号： H02M3/07
摘要： An charge pump architecture capable of generating ultra high DC voltages but implemented in low voltage CMOS technology uses a cascade of NMOS stages with the bulk terminal of the latter stages biased to a voltage just below the reverse breakdown of the parasitic bulk diode. The bias voltage is tapped from a lower voltage point within the charge pump. The upper limit of the output voltage is then increased to the maximum allowable oxide voltage plus the parasitic diode reverse bias breakdown voltage.
摘要翻译：能够产生超高直流电压但在低电压CMOS技术中实现的电荷泵架构使用级联的NMOS级，后级的体端被偏压到刚好低于寄生体二极管反向击穿的电压。偏置电压从电荷泵内的较低电压点抽头。然后将输出电压的上限提高到最大允许氧化物电压加上寄生二极管反向偏压击穿电压。

5. 发明授权

US07551009B2 High-speed divider with reduced power consumption 有权
标题翻译：高速分频器，功耗降低
公开(公告)号：US07551009B2
公开(公告)日：2009-06-23
申请号：US11680016
申请日：2007-02-28
申请人： Akhil K. Garlapati , Lizhong Sun , Douglas F. Pastorello
发明人： Akhil K. Garlapati , Lizhong Sun , Douglas F. Pastorello
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/54 , H03K19/0016
摘要： A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. The at least one of the plurality of pulse-width control circuits includes a first pulse-width control circuit to generate a first signal having the first pulse-width, second frequency, and first phase. The first signal corresponds to a select circuit output signal having a first phase. The method includes selecting at least one other of the plurality of pulse-width control circuits to be powered-off.
摘要翻译：一种用于将具有第一频率的信号除以分频比的方法包括基于分频比选择具有第二频率的至少一个信号的第一脉冲宽度，并且通过至少一个多个脉冲中的相应一个产生响应于具有第二脉冲宽度的至少一个信号的宽度控制电路。所述方法包括选择所述多个脉冲宽度控制电路中的至少一个被加电以产生所述至少一个信号。多个脉冲宽度控制电路中的至少一个包括第一脉冲宽度控制电路，用于产生具有第一脉冲宽度，第二频率和第一相位的第一信号。第一信号对应于具有第一相位的选择电路输出信号。该方法包括选择要断电的多个脉冲宽度控制电路中的至少一个。

6. 发明申请

US20080204088A1 HIGH-SPEED DIVIDER WITH REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的高速分流器
公开(公告)号：US20080204088A1
公开(公告)日：2008-08-28
申请号：US11680016
申请日：2007-02-28
申请人： Akhil K. Garlapati , Lizhong Sun , Douglas F. Pastorello
发明人： Akhil K. Garlapati , Lizhong Sun , Douglas F. Pastorello
IPC分类号： H03K21/00
CPC分类号： H03K23/54 , H03K19/0016
摘要： A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. The at least one of the plurality of pulse-width control circuits includes a first pulse-width control circuit to generate a first signal having the first pulse-width, second frequency, and first phase. The first signal corresponds to a select circuit output signal having a first phase. The method includes selecting at least one other of the plurality of pulse-width control circuits to be powered-off.
摘要翻译：一种用于将具有第一频率的信号除以分频比的方法包括基于分频比选择具有第二频率的至少一个信号的第一脉冲宽度，并且通过至少一个多个脉冲中的相应一个产生响应于具有第二脉冲宽度的至少一个信号的宽度控制电路。所述方法包括选择所述多个脉冲宽度控制电路中的至少一个被加电以产生所述至少一个信号。多个脉冲宽度控制电路中的至少一个包括第一脉冲宽度控制电路，用于产生具有第一脉冲宽度，第二频率和第一相位的第一信号。第一信号对应于具有第一相位的选择电路输出信号。该方法包括选择要断电的多个脉冲宽度控制电路中的至少一个。

7. 发明授权

US07352207B2 Output driver with common mode feedback 有权
标题翻译：具有共模反馈的输出驱动器
公开(公告)号：US07352207B2
公开(公告)日：2008-04-01
申请号：US11239944
申请日：2005-09-30
申请人： Akhil K. Garlapati , Axel Thomsen
发明人： Akhil K. Garlapati , Axel Thomsen
IPC分类号： H03K19/094 , H03K19/0175 , H01L5/00
CPC分类号： H03F3/45188 , H03F3/3061 , H03F3/45654 , H03F3/45708
摘要： A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differential output node. The load circuit may have any impedance within a particular impedance range. A current source provides a current with a variable current component that adjusts the differential voltage swing of the differential output signal. A common mode feedback circuit adjusts the common mode voltage of the differential output signal by sourcing current to the differential output node or sinking current from the differential output node. At least a portion of a current flowing into a load circuit coupled to the differential node is provided by the current source, thereby reusing current from the current source.
摘要翻译：互补金属氧化物半导体输出驱动器为耦合到差分输出节点的各种类型的负载电路提供具有特定差分电压摆幅和特定共模电压的差分输出信号到差分输出节点。负载电路可以在特定阻抗范围内具有任何阻抗。电流源为电流提供调节差分输出信号的差分电压摆幅的可变电流分量。共模反馈电路通过向差分输出节点提供电流或从差分输出节点吸收电流来调整差分输出信号的共模电压。流过耦合到差分节点的负载电路的电流的至少一部分由电流源提供，从而重新使用来自电流源的电流。

8. 发明授权

US07224210B2 Voltage reference generator circuit subtracting CTAT current from PTAT current 有权
标题翻译：电压基准发生器电路从PTAT电流中减去CTAT电流
公开(公告)号：US07224210B2
公开(公告)日：2007-05-29
申请号：US10877288
申请日：2004-06-25
申请人： Akhil K. Garlapati , David Pietruszynski , Bruce P. Del Signore
发明人： Akhil K. Garlapati , David Pietruszynski , Bruce P. Del Signore
IPC分类号： G05F1/10
CPC分类号： G05F3/267
摘要： A voltage reference generator generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has comparable noise performance as compared to traditional bandgap cirucits. These advantages are achieved by subtracting a current proportional to a complement of an absolute temperature from a current proportional to the absolute temperature to generate a voltage having a positive temperature coefficient, which is then added to a voltage that is a complement of the absolute temperature to achieve a voltage that has a low temperature coefficient.
摘要翻译：电压参考发生器产生小于2V的电源电压的硅的带隙电压的稳定的参考电压，但是为电流镜提供足够的电压余量。在一个实施例中，电压参考发生器具有至少60dB的电源抑制比，并且与传统的带隙尖端相比具有可比较的噪声性能。这些优点通过从与绝对温度成比例的电流中减去与绝对温度的互补成比例的电流来实现，以产生具有正温度系数的电压，然后将其加到作为绝对温度至达到低温系数的电压。

9. 发明授权

US07145359B2 Multiple signal format output buffer 有权
标题翻译：多信号格式输出缓冲区
公开(公告)号：US07145359B2
公开(公告)日：2006-12-05
申请号：US10878197
申请日：2004-06-28
申请人： Jerrell P. Hein , Bruce P. Del Signore , Akhil K. Garlapati
发明人： Jerrell P. Hein , Bruce P. Del Signore , Akhil K. Garlapati
IPC分类号： H03K19/173
CPC分类号： H03K19/018585
摘要： An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.
摘要翻译：输出缓冲电路驱动多种信号格式。输出缓冲电路减少了集成电路管芯上的输出接合焊盘的重复。输出缓冲电路减少了在系统板上包含转换缓冲区的需求。包括输出缓冲电路的单个集成电路可以满足各种应用。输出缓冲器通过可编程输出电压摆幅和可编程输出共模电压实现这些结果。在本发明的一些实施例中，集成电路包括耦合到一对输出的至少一个单端缓冲器和至少一个差分电路。单端缓冲器和差分电路之一被选择性地使能以向输出提供信号。

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