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1. 发明授权

US07029976B1 Method for SONOS EFLASH integrated circuit 失效
标题翻译： SONOS EFLASH集成电路方法
公开(公告)号：US07029976B1
公开(公告)日：2006-04-18
申请号：US11041051
申请日：2005-01-21
申请人： Sripad Sheshagiri Nagarad , Dong Kyun Sohn , Yoke Leng Louis Lim , Siow Lee Chwa , Hsiang Fang Lim
发明人： Sripad Sheshagiri Nagarad , Dong Kyun Sohn , Yoke Leng Louis Lim , Siow Lee Chwa , Hsiang Fang Lim
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , Y10S438/954
摘要： A method of manufacturing a charge storage layer for a SONOS memory device. A feature of the embodiment is the first gate layer is formed over the charge storing layer (ONO) before the charge storing layer is patterned. The first gate layer protects the charge storing layer (ONO) from various etches used in the process to pattern the various gate dielectric layers on other regions of substrate.
摘要翻译：一种制造用于SONOS存储器件的电荷存储层的方法。本实施例的特征是在对电荷存储层进行图案化之前，在电荷存储层（ONO）上形成第一栅极层。第一栅极层保护电荷存储层（ONO）免受在该工艺中使用的各种蚀刻，以对衬底的其它区域上的各种栅极电介质层进行图案化。

2. 发明授权

US07595237B2 Non-volatile memory cell with a hybrid access transistor 有权
标题翻译：具有混合存取晶体管的非易失性存储单元
公开(公告)号：US07595237B2
公开(公告)日：2009-09-29
申请号：US11740939
申请日：2007-04-27
申请人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
发明人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0433 , H01L21/28282 , H01L29/66833
摘要： A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.
摘要翻译：非易失性存储单元包括串联耦合的存取晶体管和存储晶体管。存储器单元形成在薄栅极上，该薄栅极具有薄栅极电介质的晶体管。存取晶体管是混合晶体管，其包括形成在薄栅极阱上的具有厚栅介电层的栅极。

3. 发明授权

US06835609B1 Method of forming double-gate semiconductor-on-insulator (SOI) transistors 有权
标题翻译：形成双栅绝缘体上半导体（SOI）晶体管的方法
公开(公告)号：US06835609B1
公开(公告)日：2004-12-28
申请号：US10664210
申请日：2003-09-17
申请人： Yong Meng Lee , Da Jin , Mau Lam Lai , David Vigar , Siow Lee Chwa
发明人： Yong Meng Lee , Da Jin , Mau Lam Lai , David Vigar , Siow Lee Chwa
IPC分类号： H01L21338
CPC分类号： H01L29/66772 , H01L29/42392 , H01L29/4908 , H01L29/78648 , H01L29/78654
摘要： A method of forming a double gated SOI channel transistor comprising the following steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI silicon oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned silicon layer. A dummy layer is formed over the SOI silicon oxide layer and the patterned SOI silicon layer. The dummy layer is patterned to form a damascene opening therein exposing: a portion of the lower SOI silicon oxide layer; and a central portion of the patterned SOI silicon layer to define a source structure and a drain structure. Patterning the exposed lower SOI silicon oxide layer to form a recess. Gate oxide layer portions are formed around the exposed portion of the patterned SOI silicon layer. A planarized layer portion is formed within the final damascene opening. The planarized layer portion including a bottom gate and a top gate. The patterned dummy layer is removed to form the double gated SOI channel transistor.
摘要翻译：一种形成双门控SOI沟道晶体管的方法，包括以下步骤。提供了具有形成在其上的SOI结构的衬底。 SOI结构包括下部SOI硅氧化物层和上部SOI硅层。图案化SOI硅层以形成图案化的硅层。在SOI氧化硅层和图案化SOI硅层上形成虚设层。图案化虚拟层以在其中形成镶嵌开口，暴露下部SOI氧化硅层的一部分; 以及图案化SOI硅层的中心部分，以限定源结构和漏极结构。对暴露的下部SOI硅氧化物层进行成形以形成凹陷。栅极氧化物层部分形成在图案化SOI硅层的暴露部分周围。平坦化层部分形成在最后的镶嵌开口内。平坦化层部分包括底部栅极和顶部栅极。去除图案化的虚拟层以形成双门控SOI沟道晶体管。

4. 发明申请

US20080266944A1 NON-VOLATILE MEMORY CELL WITH A HYBRID ACCESS TRANSISTOR 有权
标题翻译：具有混合存取晶体管的非易失性存储单元
公开(公告)号：US20080266944A1
公开(公告)日：2008-10-30
申请号：US11740939
申请日：2007-04-27
申请人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
发明人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , G11C16/0433 , H01L21/28282 , H01L29/66833
摘要： A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.
摘要翻译：非易失性存储单元包括串联耦合的存取晶体管和存储晶体管。存储器单元形成在薄栅极上，该薄栅极具有薄栅极电介质的晶体管。存取晶体管是混合晶体管，其包括形成在薄栅极阱上的具有厚栅介电层的栅极。

5. 发明授权

US07355896B2 System for improving endurance and data retention in memory devices 有权
标题翻译：用于提高存储设备中耐用性和数据保留性的系统
公开(公告)号：US07355896B2
公开(公告)日：2008-04-08
申请号：US11306331
申请日：2005-12-22
申请人： Wenbo Li , Maggie L. F. Tan , Siow Lee Chwa , Fei Xu
发明人： Wenbo Li , Maggie L. F. Tan , Siow Lee Chwa , Fei Xu
IPC分类号： G11C11/03
CPC分类号： G11C16/16 , G11C16/3477
摘要： A memory system includes a memory block having at least one memory cell. The current is sensed after the erase operations of the memory cell. A signal is generated in response to the current dropping below a predetermined level after the erase operations of the memory cell. The stress on the memory cell is reduced to a first reduced level for erase operations occurring subsequent to the current dropping below the predetermined level.
摘要翻译：存储器系统包括具有至少一个存储器单元的存储器块。在存储器单元的擦除操作之后感测电流。在存储单元的擦除操作之后，响应于电流下降到预定电平以下而生成信号。存储单元上的应力被降低到第一降低电平，用于在电流下降到预定电平之前发生的擦除操作。

6. 发明授权

US06399443B1 Method for manufacturing dual voltage flash integrated circuit 有权
标题翻译：双电压闪存集成电路的制造方法
公开(公告)号：US06399443B1
公开(公告)日：2002-06-04
申请号：US09850906
申请日：2001-05-07
申请人： Siow Lee Chwa , Yung Tao Lin
发明人： Siow Lee Chwa , Yung Tao Lin
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/981
摘要： A method is provided for manufacturing a multiple voltage flash memory integrated circuit structure on a semiconductor substrate having a plurality of shallow trench isolations and a floating gate structure. A first dielectric layer is formed and a portion removed to expose regions of the semiconductor substrate for first and second low voltage devices. A second dielectric layer is formed over the first dielectric layer and the semiconductor substrate and a portion removed to expose a region of the semiconductor substrate for the second low voltage device. A third dielectric layer is formed over the second dielectric layer to form: a floating gatedevice including the first, second, and third dielectric layers; a first voltage device including the first, second, and third dielectric layers; a second voltage device including the second and third dielectric layers; and a third voltage device including the third dielectric layer.
摘要翻译：提供了一种用于在具有多个浅沟槽隔离物和浮动栅极结构的半导体衬底上制造多电压闪存存储器集成电路结构的方法。形成第一电介质层，去除部分以暴露用于第一和第二低电压器件的半导体衬底的区域。在第一电介质层和半导体衬底之上形成第二电介质层，并且去除部分以露出用于第二低电压器件的半导体衬底的区域。在所述第二电介质层上形成第三电介质层，以形成：包括所述第一，第二和第三电介质层的浮动栅极装置; 包括所述第一，第二和第三电介质层的第一电压装置; 包括第二和第三电介质层的第二电压装置; 以及包括第三电介质层的第三电压装置。

7. 发明授权

US6147008A Creation of multiple gate oxide with high thickness ratio in flash memory process 失效
标题翻译：在闪存过程中创建高厚度比的多栅极氧化物
公开(公告)号：US6147008A
公开(公告)日：2000-11-14
申请号：US443421
申请日：1999-11-19
申请人： Siow Lee Chwa , Ying Jin , Yung-Tao Lin
发明人： Siow Lee Chwa , Ying Jin , Yung-Tao Lin
IPC分类号： H01L21/8247 , H01L21/265 , H01L21/31 , H01L21/316 , H01L21/8234 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A new method is provided for the creation of an oxide layer that contains three different thicknesses. A first layer of oxide is grown on the surface of a substrate; a first layer of photoresist is deposited and patterned thereby partially exposing the surface of the underlying first layer of oxide. A nitrogen implant is performed into the surface of the underlying substrate; the photoresist mask of the first layer of photoresist is removed. A second layer of photoresist is deposited and patterned, the first layer of oxide is removed from above and surrounding the implanted regions of the substrate. The second mask of resist is removed. The first layer of oxide is reduced in thickness, its thickness is restored to a first thickness by a blanket growth of a second layer of oxide over the exposed surface of the substrate (where no ion implant has been performed) to a third thickness, over the surface of the substrate where the ion implant has been performed to a second thickness and over the surface of the first layer of oxide thereby restoring this layer of oxide to its original first thickness.
摘要翻译：提供了一种新方法，用于产生含有三种不同厚度的氧化物层。在衬底的表面上生长第一层氧化物; 沉积和图案化第一层光致抗蚀剂，从而部分地暴露下面的第一层氧化物的表面。在下面的基底的表面上进行氮注入; 去除第一层光致抗蚀剂的光致抗蚀剂掩模。沉积和图案化第二层光致抗蚀剂，从上方去除第一层氧化物并围绕衬底的注入区域。抗蚀剂的第二个掩模被去除。第一层氧化物的厚度减小，其厚度通过在衬底的暴露表面（其中没有进行离子注入）到第三厚度的第二层氧化物的覆盖生长而恢复到第一厚度，超过已经进行离子注入的衬底的表面达到第二厚度并且在第一氧化物层的表面上，从而将该氧化物层恢复到其原始的第一厚度。

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