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1. 发明授权

US06835609B1 Method of forming double-gate semiconductor-on-insulator (SOI) transistors 有权
标题翻译：形成双栅绝缘体上半导体（SOI）晶体管的方法
公开(公告)号：US06835609B1
公开(公告)日：2004-12-28
申请号：US10664210
申请日：2003-09-17
申请人： Yong Meng Lee , Da Jin , Mau Lam Lai , David Vigar , Siow Lee Chwa
发明人： Yong Meng Lee , Da Jin , Mau Lam Lai , David Vigar , Siow Lee Chwa
IPC分类号： H01L21338
CPC分类号： H01L29/66772 , H01L29/42392 , H01L29/4908 , H01L29/78648 , H01L29/78654
摘要： A method of forming a double gated SOI channel transistor comprising the following steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI silicon oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned silicon layer. A dummy layer is formed over the SOI silicon oxide layer and the patterned SOI silicon layer. The dummy layer is patterned to form a damascene opening therein exposing: a portion of the lower SOI silicon oxide layer; and a central portion of the patterned SOI silicon layer to define a source structure and a drain structure. Patterning the exposed lower SOI silicon oxide layer to form a recess. Gate oxide layer portions are formed around the exposed portion of the patterned SOI silicon layer. A planarized layer portion is formed within the final damascene opening. The planarized layer portion including a bottom gate and a top gate. The patterned dummy layer is removed to form the double gated SOI channel transistor.
摘要翻译：一种形成双门控SOI沟道晶体管的方法，包括以下步骤。提供了具有形成在其上的SOI结构的衬底。 SOI结构包括下部SOI硅氧化物层和上部SOI硅层。图案化SOI硅层以形成图案化的硅层。在SOI氧化硅层和图案化SOI硅层上形成虚设层。图案化虚拟层以在其中形成镶嵌开口，暴露下部SOI氧化硅层的一部分; 以及图案化SOI硅层的中心部分，以限定源结构和漏极结构。对暴露的下部SOI硅氧化物层进行成形以形成凹陷。栅极氧化物层部分形成在图案化SOI硅层的暴露部分周围。平坦化层部分形成在最后的镶嵌开口内。平坦化层部分包括底部栅极和顶部栅极。去除图案化的虚拟层以形成双门控SOI沟道晶体管。

2. 发明申请

US20150200290A1 PLANAR MOSFETS AND METHODS OF FABRICATION, CHARGE RETENTION 有权
标题翻译：平面MOSFET和制造方法，充电保持
公开(公告)号：US20150200290A1
公开(公告)日：2015-07-16
申请号：US14597233
申请日：2015-01-15
申请人： Mau Lam Lai
发明人： Mau Lam Lai , Yeuk Yin Mong , Duc Quang Chau
IPC分类号： H01L29/78 , H01L29/06 , H01L29/10 , H01L29/66
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/66712 , H01L29/66825 , H01L29/7841 , H01L29/7881
摘要： A planar MOSFET includes a plurality of MOSFET cells. Each MOSFET cell includes an epitaxial layer of a first conductivity type, a body region of a second conductivity type inside the epitaxial layer, the second conductivity type having a polarity opposite to the first conductivity type, a source region inside the body region, a source contact portion to provide electrical contact with the source region, and a gate portion. A drift region is defined in the epitaxial layer between body regions of adjacent MOSFET cells and the gate portions of the adjacent MOSFET cells across said drift region are separated from each other with electrical insulation. A charge induction terminal is provided on the drift region to induce and store electric charge at said drift region upon application of a charge induction voltage at said charge induction terminal.
摘要翻译：平面MOSFET包括多个MOSFET单元。每个MOSFET单元包括第一导电类型的外延层，外延层内部的第二导电类型的体区，具有与第一导电类型相反极性的第二导电类型，体区内的源极区，源极接触部分以提供与源极区域的电接触，以及栅极部分。在相邻MOSFET单元的主体区域之间的外延层中限定漂移区域，并且跨越所述漂移区域的相邻MOSFET单元的栅极部分通过电绝缘彼此分离。在所述漂移区域上设置电荷感应端子，以在所述电荷感应端子处施加电荷感应电压时，在所述漂移区域处诱导并存储电荷。

3. 发明授权

US09466707B2 Planar mosfets and methods of fabrication, charge retention 有权
标题翻译：平面的mosfets和制造方法，电荷保留
公开(公告)号：US09466707B2
公开(公告)日：2016-10-11
申请号：US14597233
申请日：2015-01-15
申请人： Mau Lam Lai
发明人： Mau Lam Lai , Yeuk Yin Mong , Duc Quang Chau
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/788
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/66712 , H01L29/66825 , H01L29/7841 , H01L29/7881
摘要： A planar MOSFET includes a plurality of MOSFET cells. Each MOSFET cell includes an epitaxial layer of a first conductivity type, a body region of a second conductivity type inside the epitaxial layer, the second conductivity type having a polarity opposite to the first conductivity type, a source region inside the body region, a source contact portion to provide electrical contact with the source region, and a gate portion. A drift region is defined in the epitaxial layer between body regions of adjacent MOSFET cells and the gate portions of the adjacent MOSFET cells across said drift region are separated from each other with electrical insulation. A charge induction terminal is provided on the drift region to induce and store electric charge at said drift region upon application of a charge induction voltage at said charge induction terminal.
摘要翻译：平面MOSFET包括多个MOSFET单元。每个MOSFET单元包括第一导电类型的外延层，外延层内部的第二导电类型的体区，具有与第一导电类型相反的极性的第二导电类型，体区内的源极区，源极接触部分以提供与源极区域的电接触，以及栅极部分。在相邻MOSFET单元的主体区域之间的外延层中限定漂移区域，并且跨越所述漂移区域的相邻MOSFET单元的栅极部分通过电绝缘彼此分离。在所述漂移区域上设置电荷感应端子，以在所述电荷感应端子处施加电荷感应电压时，在所述漂移区域处诱导并存储电荷。

4. 发明授权

US06177304B1 Self-aligned contact process using a poly-cap mask 失效
标题翻译：使用多盖罩罩的自对准接触过程
公开(公告)号：US06177304B1
公开(公告)日：2001-01-23
申请号：US09298933
申请日：1999-04-26
申请人： Weining Li , Yung-Tao Lin , Mau Lam Lai , Tin Tin Wee
发明人： Weining Li , Yung-Tao Lin , Mau Lam Lai , Tin Tin Wee
IPC分类号： H01L218238
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823475 , H01L21/823481
摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. Gate electrodes and associated source and drain regions are formed on and in the semiconductor substrate wherein the gate electrodes have silicon nitride sidewall spacers. A metal silicide layer is formed on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source and drain regions associated with the gate electrodes using a salicide process. A poly-cap layer is deposited overlying the substrate. The poly-cap layer is selectively removed overlying one of the salicided source and drain regions where a self-aligned contact is to be formed, and overlying another of the salicided source and drain regions and a portion of its associated salicided gate electrode where a butted contact is to be formed. An insulating layer is deposited over the surface of the semiconductor substrate. The insulating layer is etched through to form simultaneously the planned self-aligned contact opening and the planned butted contact opening. The self-aligned contact opening and the butted contact opening are filled with a conducting layer to complete fabrication of the integrated circuit device.
摘要翻译：描述了在具有嵌入式存储器的逻辑电路的制造中整合自杀化和自对准接触过程的方法。隔离区域形成在围绕并电隔离器件区域的半导体衬底上。栅极电极和相关的源极和漏极区域形成在半导体衬底上和栅极中具有氮化硅侧壁间隔物。使用自对准硅化物工艺在栅电极的顶表面和半导体衬底的顶表面上形成金属硅化物层，覆盖与栅电极相关的源极和漏极区域。多层覆盖层沉积在衬底上。选择性地去除聚盖层，覆盖其中要形成自对准接触的水银源区和漏区之一，并且覆盖另一个水银源和漏区及其相关联的盐化栅极的一部分，其中对接接触将被形成。绝缘层沉积在半导体衬底的表面上。绝缘层被蚀刻通过以形成计划的自对准接触开口和计划的对接接触开口。自对准的接触开口和对接的接触开口填充有导电层，以完成集成电路器件的制造。

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