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1. 发明授权

US07595237B2 Non-volatile memory cell with a hybrid access transistor 有权
标题翻译：具有混合存取晶体管的非易失性存储单元
公开(公告)号：US07595237B2
公开(公告)日：2009-09-29
申请号：US11740939
申请日：2007-04-27
申请人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
发明人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0433 , H01L21/28282 , H01L29/66833
摘要： A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.
摘要翻译：非易失性存储单元包括串联耦合的存取晶体管和存储晶体管。存储器单元形成在薄栅极上，该薄栅极具有薄栅极电介质的晶体管。存取晶体管是混合晶体管，其包括形成在薄栅极阱上的具有厚栅介电层的栅极。

2. 发明申请

US20080266944A1 NON-VOLATILE MEMORY CELL WITH A HYBRID ACCESS TRANSISTOR 有权
标题翻译：具有混合存取晶体管的非易失性存储单元
公开(公告)号：US20080266944A1
公开(公告)日：2008-10-30
申请号：US11740939
申请日：2007-04-27
申请人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
发明人： Xiaoyu Chen , Donghua Liu , Sung Mun Jung , Swee Tuck Woo , Rachel Low , Louis Lim , Siow Lee Chwa
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , G11C16/0433 , H01L21/28282 , H01L29/66833
摘要： A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.
摘要翻译：非易失性存储单元包括串联耦合的存取晶体管和存储晶体管。存储器单元形成在薄栅极上，该薄栅极具有薄栅极电介质的晶体管。存取晶体管是混合晶体管，其包括形成在薄栅极阱上的具有厚栅介电层的栅极。

3. 发明授权

US07332378B2 Integrated circuit memory system with dummy active region 有权
标题翻译：具有虚拟有源区的集成电路存储器系统
公开(公告)号：US07332378B2
公开(公告)日：2008-02-19
申请号：US11308061
申请日：2006-03-04
申请人： Sung Mun Jung , Ching Dong Wang , Louis Yoke Leng Lim , Swee Tuck Woo , Donghua Liu , Xiaoyu Chen
发明人： Sung Mun Jung , Ching Dong Wang , Louis Yoke Leng Lim , Swee Tuck Woo , Donghua Liu , Xiaoyu Chen
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/11568
摘要： An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.
摘要翻译：一种集成电路存储器系统，包括形成有等间隔开的浅沟槽隔离区域的衬底。在等离子间隔开的浅沟槽隔离区域之间的衬底内形成有源区和虚拟有源区。在活跃区域内形成源头和排水渠。提供在第一方向上延伸的字线和源极线，并且沿第二方向延伸的位线。在虚拟有源区域上形成接触区域，用于将字线和源极线捆扎到位线。

4. 发明申请

US20070207558A1 INTEGRATED CIRCUIT MEMORY SYSTEM WITH DUMMY ACTIVE REGION 有权
标题翻译：集成电路存储器系统与DUMMY活动区域
公开(公告)号：US20070207558A1
公开(公告)日：2007-09-06
申请号：US11308061
申请日：2006-03-04
申请人： Sung Mun Jung , Ching Dong Wang , Louis Yoke Leng Lim , Swee Tuck Woo , Donghua Liu , Xiaoyu Chen
发明人： Sung Mun Jung , Ching Dong Wang , Louis Yoke Leng Lim , Swee Tuck Woo , Donghua Liu , Xiaoyu Chen
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , H01L27/11568
摘要： An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.
摘要翻译：一种集成电路存储器系统，包括形成有等间隔开的浅沟槽隔离区域的衬底。在等离子间隔开的浅沟槽隔离区域之间的衬底内形成有源区和虚拟有源区。在活跃区域内形成源头和排水渠。提供在第一方向上延伸的字线和源极线，并且沿第二方向延伸的位线。在虚拟有源区域上形成接触区域，用于将字线和源极线捆扎到位线。

5. 发明授权

US08383475B2 EEPROM cell 有权
标题翻译： EEPROM单元
公开(公告)号：US08383475B2
公开(公告)日：2013-02-26
申请号：US12888431
申请日：2010-09-23
申请人： Sung Mun Jung , Kian Hong Lim , Jianbo Yang , Swee Tuck Woo , Sanford Chu
发明人： Sung Mun Jung , Kian Hong Lim , Jianbo Yang , Swee Tuck Woo , Sanford Chu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.
摘要翻译：公开了一种形成装置的方法。该方法包括提供制备有由其它活性区域隔离的细胞区域的基底。在单元区域中形成第一和第二晶体管的第一和第二栅极。第一栅极包括由第一隔间栅极介电层隔开的第一和第二子栅极。第二栅极包括围绕第一子栅极的第二子栅极。第二栅极的第一和第二子栅极由第二栅极间介电层分开。形成第一和第二晶体管的第一和第二结。该方法还包括形成耦合到第一晶体管的第二子栅极的第一栅极端子和耦合到第二晶体管的至少第一子栅极的第二栅极端子。

6. 发明授权

US08383476B2 EEPROM cell 有权
标题翻译： EEPROM单元
公开(公告)号：US08383476B2
公开(公告)日：2013-02-26
申请号：US12888437
申请日：2010-09-23
申请人： Sung Mun Jung , Kian Hong Lim , Jianbo Yang , Swee Tuck Woo , Sanford Chu
发明人： Sung Mun Jung , Kian Hong Lim , Jianbo Yang , Swee Tuck Woo , Sanford Chu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.
摘要翻译：公开了一种形成装置的方法。该方法包括提供准备有单元区域的基板，并在单元区域中形成第一和第二晶体管的第一和第二栅极。第一栅极包括围绕第一子栅极的第二子栅极。第一栅极的第一和第二子栅极由第一栅极介电层分开。第二栅极包括围绕第一子栅极的第二子栅极。第二栅极的第一和第二子栅极由第二栅极间介电层分开。该方法还包括形成第一和第二晶体管的第一和第二结。第一栅极端子形成并耦合到第一晶体管的第二子栅极。第二栅极端子形成并耦合到至少第二晶体管的第一子栅极。

7. 发明授权

US08541273B2 Dielectric stack 有权
标题翻译：电介质堆
公开(公告)号：US08541273B2
公开(公告)日：2013-09-24
申请号：US12888434
申请日：2010-09-23
申请人： Sung Mun Jung , Swee Tuck Woo , Sanford Chu , Liang Choo Hsia
发明人： Sung Mun Jung , Swee Tuck Woo , Sanford Chu , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L29/511 , H01L21/02326 , H01L21/28282 , H01L22/12 , H01L22/20 , H01L29/792
摘要： A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.
摘要翻译：公开了一种形成装置的方法。该方法包括提供衬底并在具有成形厚度TFD的衬底上形成器件层。在具有成形厚度TFC的基板上形成覆盖层。形成覆盖层消耗所需量的器件层，以使器件层的厚度达到目标厚度TTD。将覆盖层的厚度从TFC调整到大约目标厚度TTC。

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