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1. 发明授权

US07013401B2 Processor capable of preventing sleep/hold state based on a difference between a processing block address and a writing block address 失效
标题翻译：处理器能够基于处理块地址和写入块地址之间的差异来防止睡眠/保持状态
公开(公告)号：US07013401B2
公开(公告)日：2006-03-14
申请号：US10234857
申请日：2002-09-05
申请人： Shiro Shimizu , Tsuyoshi Takayama , Hiroshi Yasuda
发明人： Shiro Shimizu , Tsuyoshi Takayama , Hiroshi Yasuda
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F9/30 , G06F1/04 , G06F1/3203 , G06F1/3237 , G06F9/3869 , Y02D10/128 , Y02D50/20
摘要： The present invention provides a clock control type processor which can permit and accommodate a temporary delay in a processing operation also in a system in which processing times are not constant, and realize the accommodation while reducing the power consumption as much as possible. In this clock control type processor, a block difference detection circuit 20 detects a difference between a processing block address and a writing block address and outputs a block difference signal 105, and a clock control circuit 16 controls a clock.
摘要翻译：本发明提供了一种时钟控制型处理器，其可以在处理时间不恒定的系统中允许和适应处理操作中的暂时延迟，并且尽可能地减少功耗实现住宿。在该时钟控制型处理器中，块差分检测电路20检测处理块地址和写入块地址之间的差异，并输出块差信号105，时钟控制电路16控制时钟。

2. 发明授权

US08536002B2 Bipolar transistor in bipolar-CMOS technology 有权
标题翻译：双极晶体管在双极CMOS技术
公开(公告)号：US08536002B2
公开(公告)日：2013-09-17
申请号：US13567552
申请日：2012-08-06
申请人： Hiroshi Yasuda , Berthold Staufer
发明人： Hiroshi Yasuda , Berthold Staufer
IPC分类号： H01L21/8238
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/1004 , H01L29/66287 , H01L29/732 , H01L29/7833
摘要： A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.
摘要翻译：通过使用非选择性外延工艺形成双极型晶体管的基极层，使得基极层在集电极有源区域上具有单一结晶区域和多晶硅层，形成包含双极晶体管和MOS晶体管的集成电路的工艺区域，并且同时注入基极层的MOS栅极层和多晶区域，使得基极 - 集电极结延伸到小于场氧化物深度的三分之一的衬底中，并且垂直累积掺杂基极层的多晶区域的密度在MOS栅极的垂直累积掺杂密度的80％至125％之间。包含双极晶体管和通过所描述的工艺形成的MOS晶体管的集成电路。

3. 发明授权

US08450179B2 Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication 有权
标题翻译：具有第一双极器件和第二双极器件的半导体器件及其制造方法
公开(公告)号：US08450179B2
公开(公告)日：2013-05-28
申请号：US11670729
申请日：2007-02-02
申请人： Badih El-Kareh , Hiroshi Yasuda , Scott Balster
发明人： Badih El-Kareh , Hiroshi Yasuda , Scott Balster
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L21/8222 , H01L21/8249 , H01L27/0825 , H01L29/66242
摘要： A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.
摘要翻译：一种用于制造具有相同掺杂剂类型的第一和第二双极器件的半导体器件的方法包括：在半导体层上沉积介电层，在电介质层上沉积栅极导体层，限定两个双极器件的基极区域，栅极导体层和电介质层，在栅极导体层和基极区域的暴露的半导体层上沉积基底层，在基底层上沉积绝缘层，形成光致抗蚀剂层并限定两者的发射极区域去除发射极区域中的光致抗蚀剂层，从而形成两个发射器窗口，掩蔽第一双极器件的发射极窗口，并将第二双极器件的基极区域中的基极层通过相关的发射极窗口暴露于另外的发射体注入。

4. 发明授权

US08222619B2 Multi-column electron beam exposure apparatus and multi-column electron beam exposure method 有权
标题翻译：多列电子束曝光装置和多列电子束曝光方法
公开(公告)号：US08222619B2
公开(公告)日：2012-07-17
申请号：US12586717
申请日：2009-09-25
申请人： Akio Yamada , Hiroshi Yasuda , Mitsuhiro Nakano , Takashi Kiuchi
发明人： Akio Yamada , Hiroshi Yasuda , Mitsuhiro Nakano , Takashi Kiuchi
IPC分类号： A61N5/00 , G21G5/00
CPC分类号： B82Y40/00 , B82Y10/00 , H01J37/3045 , H01J37/3174 , H01J37/3177 , H01J2237/24507 , H01J2237/24521 , H01J2237/24535 , H01J2237/24542
摘要： A multi-column electron beam exposure apparatus includes: a plurality of column cells; a wafer stage including an electron-beam-property detecting unit for measuring an electron beam property; and a controller for measuring beam properties of electron beams used in all the column cells by using the electron-beam-property detecting unit, and for adjusting the electron beams of the respective column cells so that the properties of the electron beams used in the column cells may be approximately identical. The electron beam property may be any of a beam position, a beam intensity, and a beam shape of the electron beam to be emitted. The electron-beam-property detecting unit may be a chip for calibration with a reference mark formed thereon or a Faraday cup.
摘要翻译：多列电子束曝光装置包括：多个柱单元; 包括用于测量电子束特性的电子束特性检测单元的晶片台; 以及用于通过使用电子束特性检测单元来测量在所有列单元中使用的电子束的光束特性的控制器，并且用于调节各列电池的电子束，使得在列中使用的电子束的性质细胞可以大致相同。电子束特性可以是要发射的电子束的光束位置，光束强度和光束形状中的任何一个。电子束特性检测单元可以是用于在其上形成有参考标记的校准芯片或法拉第杯。

5. 发明申请

US20110226967A1 Electron beam lithography apparatus and electron beam lithography method 有权
标题翻译：电子束光刻设备和电子束光刻法
公开(公告)号：US20110226967A1
公开(公告)日：2011-09-22
申请号：US13068995
申请日：2011-05-25
申请人： Akio Yamada , Tomohiro Sakazaki , Hiroshi Yasuda
发明人： Akio Yamada , Tomohiro Sakazaki , Hiroshi Yasuda
IPC分类号： G21K5/00
CPC分类号： H01J37/3175 , B82Y10/00 , B82Y40/00 , H01J37/3174
摘要： An electron beam lithography apparatus includes a storage for storing data on a drawing pattern assigned a rank based on an accuracy required for a device pattern, a drawing pattern adjustment unit to generate data on divided drawing patterns based on the rank, a settlement wait time adjustment unit to determine a settlement wait time based on the rank, and a controller to draw the device pattern while irradiating an electron beam based on the data on the divided drawing patterns and the settlement wait time. The drawing pattern adjustment unit determines upper limits on the long-side length of a divided drawing pattern or on the area of the divided drawing pattern based on the rank, and divides the drawing pattern based on the upper limits.
摘要翻译：一种电子束光刻设备，包括：存储器，用于根据设备图案所要求的准确度，对分配了等级的绘图图形进行数据存储;绘图模式调整单元，基于该等级生成分割图形的数据;结算等待时间调整基于等级确定结算等待时间的单元，以及基于划分的绘图图案和结算等待时间的数据来照射电子束时绘制设备图案的控制器。绘制图案调整单元基于等级来确定分割绘制图案的长边长度的上限或划分的绘制图案的区域的上限，并且基于上限划分绘图图案。

6. 发明申请

US20110057289A1 Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing 有权
标题翻译：使用ALD和高温短时退火的超短发射体形成
公开(公告)号：US20110057289A1
公开(公告)日：2011-03-10
申请号：US12718142
申请日：2010-03-05
申请人： Rick L. Wise , Hiroshi Yasuda
发明人： Rick L. Wise , Hiroshi Yasuda
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/36 , H01L21/02063 , H01L21/2254 , H01L29/66242 , H01L29/66272 , H01L29/73 , H01L29/7325
摘要： An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
摘要翻译：一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

7. 发明授权

US07847272B2 Electron beam exposure mask, electron beam exposure method, and electron beam exposure system 有权
标题翻译：电子束曝光掩模，电子束曝光法和电子束曝光系统
公开(公告)号：US07847272B2
公开(公告)日：2010-12-07
申请号：US11235422
申请日：2005-09-26
申请人： Hiroshi Yasuda , Akio Yamada
发明人： Hiroshi Yasuda , Akio Yamada
IPC分类号： A61N5/00
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , G03F1/20 , H01J2237/31769
摘要： An electron beam exposure system is designed to correct a proximity effect. The electron beam exposure system includes: an electron beam generation unit for generating an electron beam; an electron beam exposure mask having opening portions that are arranged so that sizes of the opening portions change at a predetermined rate in order of arrangement; a mask deflection unit for deflecting the electron beam on the electron beam exposure mask; a substrate deflection unit for deflecting and projecting the electron beam onto a substrate; and a control unit for controlling deflection amounts in the mask deflection unit and the substrate deflection unit. The direction or directions of the change may be any one of a row direction and a column direction or may be the row and column directions.
摘要翻译：电子束曝光系统设计用于校正邻近效应。电子束曝光系统包括：用于产生电子束的电子束产生单元; 电子束曝光掩模，其具有开口部，其设置成使得开口部的尺寸按照布置的顺序以预定的速率变化; 用于使电子束在电子束曝光掩模上偏转的掩模偏转单元; 用于将电子束偏转和投影到衬底上的衬底偏转单元; 以及用于控制掩模偏转单元和基板偏转单元中的偏转量的控制单元。改变的方向或方向可以是行方向和列方向中的任何一个，或者可以是行和列方向。

8. 发明授权

US07772057B2 Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权
标题翻译：具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路
公开(公告)号：US07772057B2
公开(公告)日：2010-08-10
申请号：US11470760
申请日：2006-09-07
申请人： Badih El-Kareh , Scott Gerard Balster , Hiroshi Yasuda , Manfred Schiekofer
发明人： Badih El-Kareh , Scott Gerard Balster , Hiroshi Yasuda , Manfred Schiekofer
IPC分类号： H01L21/337
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0251 , H01L27/0705
摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
摘要翻译：具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接结构体。形成身体接触结构的基层也形成双极器件的基部。本发明还涉及一种用于制造这种集成电路的方法。

9. 发明授权

US07658774B2 Method of producing lattice body for lead storage battery, and lead storage battery 有权
标题翻译：铅蓄电池晶格体生产方法及铅蓄电池
公开(公告)号：US07658774B2
公开(公告)日：2010-02-09
申请号：US10543699
申请日：2004-02-23
申请人： Kazutoshi Itagawa , Masayoshi Yuki , Hiroshi Yasuda , Yoshihiro Murata
发明人： Kazutoshi Itagawa , Masayoshi Yuki , Hiroshi Yasuda , Yoshihiro Murata
IPC分类号： H01M4/82 , H01M6/00 , H01M4/00 , H01M4/02 , B23P13/00
CPC分类号： H01M4/82 , H01M4/20 , H01M4/685 , H01M4/73 , H01M10/128 , Y10T29/10 , Y10T29/49108 , Y10T29/49114
摘要： A method of producing a grid for a lead-acid battery in accordance with the present invention includes the step of placing lead alloy foil on a base material sheet of a lead-calcium alloy and attaching the lead alloy foil under pressure to the base material sheet. The thickness t of the lead alloy foil, the thickness a of the base material sheet before the attaching, and the thickness b of the composite sheet after the attaching satisfy the relational expression 1.3≦(a+t)/b. The length L of the contact part of rollers with the base material sheet and the lead alloy foil is 10 mm or more.This makes it possible to secure good adhesion of the lead alloy foil to the base material sheet. Also, when this composite sheet is subjected to an expanding process and used as a positive electrode grid, it is possible to provide a lead-acid battery having excellent cycle life characteristics.
摘要翻译：根据本发明的铅酸蓄电池栅格的制造方法包括将铅合金箔放置在铅 - 钙合金的基材片上并将铅合金箔在压力下附着在基材片上的工序。铅合金箔的厚度t，附着前的基材片的厚度a和贴附后的复合片的厚度b满足关系式1.3 <=（a + t）/ b。与基材片和铅合金箔的辊的接触部的长度L为10mm以上。这使得可以确保铅合金箔对基材片的良好粘附性。此外，当该复合片材经受膨胀工艺并用作正极栅极时，可以提供具有优异的循环寿命特性的铅酸电池。

10. 发明申请

US20080292732A1 Plant and Plant Storage Organ Having Glp-1 Derivative Accumulated Therein and Method of Producing the Same 失效
标题翻译：含有Glp-1衍生物的植物和植物储存器官及其生产方法
公开(公告)号：US20080292732A1
公开(公告)日：2008-11-27
申请号：US11662650
申请日：2004-09-14
申请人： Koichi Sugita , Saori Kasahara , Hiroyasu Ebinuma , Fumio Takaiwa , Hiroshi Yasuda , Takahito Jomori , Yuji Hayashi , Akira Tashita
发明人： Koichi Sugita , Saori Kasahara , Hiroyasu Ebinuma , Fumio Takaiwa , Hiroshi Yasuda , Takahito Jomori , Yuji Hayashi , Akira Tashita
IPC分类号： A61K36/00 , C12N15/82 , A01H5/00 , A61P31/10
CPC分类号： A61K38/26 , A23L33/105 , C12N15/8257
摘要： The present invention is to provide a plant and a plant storage organ thereof in which GLP-1 derivatives are accumulated, and a method of producing them in order to develop a method for ingesting orally GLP-1 derivatives at a low cost and to make use of it in diabetic treatment. A transgenic plant or a plant storage organ thereof in which GLP-1 derivatives are accumulated cleavable with a digestive enzyme is produced by a method comprising: integrating into a vector a linked GLP-1s-DNA which comprises tandem repeated “n” DNAs (“n” being an integer of 3 or more) encoding a GLP-1 derivative consisting of GLP-1 (7-36) or of an amino acid sequence of GLP-1 (7-36) in which one or a few amino acids are deleted, substituted and/or added, and C-terminal consists of Arg or Lys, and having GLP-1 activity; introducing the vector into a plant cell; and redifferentiating the obtained transformant. The transgenic plant and the plant storage organ are useful as a pharmaceutical composition or a food or drink for treating or preventing diabetes.
摘要翻译：本发明提供一种其中积聚有GLP-1衍生物的植物和植物贮藏器官及其生产方法，以便开发低成本摄取口服GLP-1衍生物的方法并使用的糖尿病治疗。 GLP-1衍生物可以用消化酶积聚可切割的转基因植物或植物贮藏器官是通过以下方法产生的：将连接的GLP-1s-DNA整合到载体中，所述连接的GLP-1s-DNA包含串联重复的“n”DNA（“ 编号由GLP-1（7-36）或GLP-1（7-36）的氨基酸序列组成的GLP-1衍生物的n“为3以上的整数，其中一个或几个氨基酸为缺失，取代和/或添加，C-末端由Arg或Lys组成，具有GLP-1活性; 将载体导入植物细胞; 并对所得转化体进行重新分化。转基因植物和植物贮藏器官可用作药物组合物或用于治疗或预防糖尿病的食物或饮料。

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