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1. 发明授权

US08618633B2 Semiconductor-on-insulator apparatus, device and system with buried decoupling capacitors 有权
标题翻译：绝缘体上半导体器件，具有埋入去耦电容器的器件和系统
公开(公告)号：US08618633B2
公开(公告)日：2013-12-31
申请号：US13357322
申请日：2012-01-24
申请人： Badih El-Kareh
发明人： Badih El-Kareh
IPC分类号： H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L23/5223 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.
摘要翻译：提供了一种埋地去耦电容器装置和方法。根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

2. 发明授权

US07615425B2 Open source/drain junction field effect transistor 有权
标题翻译：开路/漏极结场效应晶体管
公开(公告)号：US07615425B2
公开(公告)日：2009-11-10
申请号：US11504412
申请日：2006-08-15
申请人： Joe R. Trogolo , Hiroshi Yasuda , Badih El-Kareh , Philipp Steinmann
发明人： Joe R. Trogolo , Hiroshi Yasuda , Badih El-Kareh , Philipp Steinmann
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0607 , H01L29/66901
摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
摘要翻译：本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作。开路漏极允许电压增加几倍，而不增加晶体管的尺寸。开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。

3. 发明授权

US07498639B2 Integrated BiCMOS semiconductor circuit 有权
标题翻译：集成BiCMOS半导体电路
公开(公告)号：US07498639B2
公开(公告)日：2009-03-03
申请号：US11233960
申请日：2005-09-23
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
IPC分类号： H01L31/112
CPC分类号： H01L27/0623 , H01L21/76229 , H01L21/8249 , H01L27/0207
摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.
摘要翻译：集成的BiCMOS半导体电路在硅中具有积极的护城河区域。活动的护壕区域包括半导体电路的电活性部件，其包括用于基底和/或发射器窗口的有源窗口结构。集成的BiCMOS半导体电路具有区域，其中硅留下以形成不包括电活性部件的虚拟护城河区域，并且具有隔离沟槽以将活动的护壕区域彼此分开并与虚拟的护城河区域分离。虚拟护城河区域包括具有几何尺寸和形状的虚拟窗户结构，其类似于用于基座和/或发射器窗口的活动窗口结构的几何尺寸和形状。

4. 发明申请

US20080042199A1 Open source/drain junction field effect transistor 有权
标题翻译：开路/漏极结场效应晶体管
公开(公告)号：US20080042199A1
公开(公告)日：2008-02-21
申请号：US11504412
申请日：2006-08-15
申请人： Joe R. Trogolo , Hiroshi Yasuda , Badih El-Kareh , Philipp Steinmann
发明人： Joe R. Trogolo , Hiroshi Yasuda , Badih El-Kareh , Philipp Steinmann
IPC分类号： H01L27/12
CPC分类号： H01L29/808 , H01L29/0607 , H01L29/66901
摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
摘要翻译：本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作。开路漏极允许电压增加几倍，而不增加晶体管的尺寸。开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。

5. 发明授权

US07192838B2 Method of producing complementary SiGe bipolar transistors 有权
标题翻译：制造互补SiGe双极晶体管的方法
公开(公告)号：US07192838B2
公开(公告)日：2007-03-20
申请号：US10928655
申请日：2004-08-26
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/82285 , H01L29/7378
摘要： Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
摘要翻译：制造互补SiGe双极晶体管的方法。在制造互补SiGe双极晶体管的方法中，分别形成用于NPN和PNP发射极（44,64）的界面氧化物层（38,58），发射极多晶硅（40,60）被分开构图，允许这些层被优化对于各自的导电类型。

6. 发明申请

US20050118771A1 Control of phosphorus profile by carbon in-situ doping for high performance vertical PNP transistor 审中-公开
标题翻译：通过碳原位掺杂控制磷分布，用于高性能垂直PNP晶体管
公开(公告)号：US20050118771A1
公开(公告)日：2005-06-02
申请号：US10978074
申请日：2004-10-28
申请人： Hiroshi Yasuda , Badih El-Kareh , Scott Balster , Manfred Schiekofer
发明人： Hiroshi Yasuda , Badih El-Kareh , Scott Balster , Manfred Schiekofer
IPC分类号： H01L21/331 , H01L29/10 , H01L29/73 , H01L29/732 , H01L29/737 , H01L21/425 , H01L21/8222
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A method of producing a vertical bipolar PNP transistor is disclosed. The phosphorous profile in the base layer is controlled. Carbon that is incorporated in the base layer in the vicinity of the base-collector junction suppresses the diffusion of phosphorous deeper than implanted in a subsequent thermal step. PNP transistors with a narrow phosphorous-doped base can thus be manufactured with a cut-off frequency increased from 23 GHz to 30 GHz.
摘要翻译：公开了一种制造垂直双极PNP晶体管的方法。控制基层中的磷分布。在底部 - 集电极结附近并入基底层中的碳，抑制磷的扩散比在随后的热步骤中植入更深。因此可以制造具有从23GHz至30GHz的截止频率的具有窄磷掺杂基极的PNP晶体管。

7. 发明申请

US20050014341A1 Method of fabricating complementary bipolar transistors with SiGe base regions 有权
标题翻译：用SiGe基极区制造互补双极晶体管的方法
公开(公告)号：US20050014341A1
公开(公告)日：2005-01-20
申请号：US10822078
申请日：2004-04-08
申请人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
发明人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
IPC分类号： H01L21/331 , H01L21/8228
CPC分类号： H01L29/66242 , H01L21/82285
摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
摘要翻译：在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过晶体硅 - 锗层32a，36a的外延沉积而在两个集电极区域20,14之间一个接一个地形成。使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。

8. 发明申请

US20050001236A1 Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor 有权
标题翻译：制造集成硅 - 锗异双极晶体管和集成硅 - 锗异双极晶体管的方法
公开(公告)号：US20050001236A1
公开(公告)日：2005-01-06
申请号：US10824745
申请日：2004-04-15
申请人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
发明人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
IPC分类号： H01L21/331 , H01L21/8222 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/7378
摘要： In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.
摘要翻译：在制造集成硅 - 锗异质晶体管的方法中，通过快速热处理（RTP）形成布置在硅 - 锗基底层和硅发射极层之间的二氧化硅层，以确保集成硅 - 锗异双极晶体管。

9. 发明授权

US06426544B1 Flexible interconnections with dual-metal dual-stud structure 失效
标题翻译：双金属双螺柱结构的柔性互连
公开(公告)号：US06426544B1
公开(公告)日：2002-07-30
申请号：US09351440
申请日：1999-07-12
申请人： James G. Ryan , Badih El-Kareh
发明人： James G. Ryan , Badih El-Kareh
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L21/76838 , H01L23/5223 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (such as TI/CuAlSi) with a dielectric interposed therebetween and a connection made between the layers by a conductive material, preferably in the form of a plug or stud formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.
摘要翻译：具有高导电性和高金属迁移破坏性的金属互连由两层金属或合金（例如TI / CuAlSi）形成，其中介电介质介于两者之间，并且通过导电材料形成在该层之间的连接，优选在在互连的端部形成在层间电介质的孔中的插头或螺柱的形式。通过与每个层形成单独的连接，可以从相同的层形成高精度的金属 - 金属电容器。互连（和电容器）的形状具有降低的严重性，并且有助于覆盖层间电介质的平坦化。

10. 发明授权

US5923999A Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device 失效
标题翻译：控制mosfet器件薄多晶硅栅极导体中掺杂剂扩散和金属污染的方法
公开(公告)号：US5923999A
公开(公告)日：1999-07-13
申请号：US741159
申请日：1996-10-29
申请人： Karanam Balasubramanyam , Stephen Bruce Brodsky , Richard Anthony Conti , Badih El-Kareh
发明人： Karanam Balasubramanyam , Stephen Bruce Brodsky , Richard Anthony Conti , Badih El-Kareh
IPC分类号： H01L29/43 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/28061 , H01L29/4941 , H01L29/6656 , H01L2924/0002 , Y10S257/916
摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.
摘要翻译：在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。栅电极包括一叠层。在栅氧化层上形成多晶硅层。在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

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