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1. 发明授权

US06661692B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06661692B2
公开(公告)日：2003-12-09
申请号：US10179710
申请日：2002-06-24
申请人： Shinsuke Anzai , Kenji Kamei , Yasumichi Mori
发明人： Shinsuke Anzai , Kenji Kamei , Yasumichi Mori
IPC分类号： G11C506
CPC分类号： G11C29/80 , G11C15/00 , G11C15/046 , H01L27/0207
摘要： A semiconductor integrated circuit of the present invention includes: n first output circuits and m second output circuits which are provided such that adjacent first and second output circuits are spaced at a regular first pitch; and input circuits which are provided such that adjacent input circuits are spaced at a regular second pitch, in which the first and second output circuits are provided such that at least part of ones of the first and second output circuit blocks alternate with the other ones of the first and second output circuits and each of the first output circuits is connected to a corresponding one of input circuits by a first conductor line which is kept straight, and second conductor lines are connected to the second output circuits such that each second conductor line passes through a gap between the input circuits.
摘要翻译：本发明的半导体集成电路包括：n个第一输出电路和m个第二输出电路，其被设置成使得相邻的第一和第二输出电路以规则的第一间距间隔开; 以及输入电路，其被设置为使得相邻输入电路以规则的第二间距间隔开，其中第一和第二输出电路被设置成使得第一和第二输出电路块中的至少一部分与其他第一和第二输出电路和第一输出电路中的每一个通过保持直的第一导体线连接到相应的一个输入电路，并且第二导体线连接到第二输出电路，使得每个第二导线通过通过输入电路之间的间隙。

2. 发明申请

US20050174868A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050174868A1
公开(公告)日：2005-08-11
申请号：US11051139
申请日：2005-02-04
申请人： Shinsuke Anzai , Yasumichi Mori
发明人： Shinsuke Anzai , Yasumichi Mori
IPC分类号： G11C16/02 , G11C11/56 , G11C13/00 , G11C16/06 , G11C16/28 , G11C16/34 , G11C11/34
CPC分类号： G11C16/28 , G11C11/5642 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C16/3436 , G11C2013/0054 , G11C2213/31
摘要： A nonvolatile semiconductor memory device comprises a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.
摘要翻译：非易失性半导体存储器件包括读出电路，其通过向所选择的存储单元施加预定电压来读取存储在所选择的存储单元中的数据，以及参考单元，使得可以流过对应于相应阈值电压的电流，并且比较流过选定的存储单元，电流在参考单元中流动。读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选存储单元和参考存储单元时验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。

3. 发明授权

US07020037B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07020037B2
公开(公告)日：2006-03-28
申请号：US11051139
申请日：2005-02-04
申请人： Shinsuke Anzai , Yasumichi Mori
发明人： Shinsuke Anzai , Yasumichi Mori
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C16/3436 , G11C2013/0054 , G11C2213/31
摘要： A nonvolatile semiconductor memory device includes a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.
摘要翻译：非易失性半导体存储器件包括：读出电路，通过向所选择的存储单元施加预定电压，读取存储在所选择的存储单元中的数据;以及参考单元，使得与各个阈值电压相对应的电流可以流动，选定的存储单元，电流在参考单元中流动。读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选择的存储单元和参考存储单元时验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。

4. 发明授权

US06947322B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06947322B2
公开(公告)日：2005-09-20
申请号：US10630641
申请日：2003-07-29
申请人： Shinsuke Anzai , Yasumichi Mori , Hidehiko Tanaka
发明人： Shinsuke Anzai , Yasumichi Mori , Hidehiko Tanaka
IPC分类号： G06F12/16 , G11C11/56 , G11C16/00 , G11C16/02 , G11C16/06 , G11C16/28 , G11C29/00 , G11C29/04 , G11C16/04
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28 , G11C29/70 , G11C2211/5623 , G11C2211/5641
摘要： A semiconductor memory device is provided, which comprising a memory cell array comprising a two-value memory region and a multi-value memory region, in which the two-value memory region comprises a plurality of memory cells each storing 1-bit data and the multi-value memory region comprises a plurality of memory cells each storing 2 or more-bit data, and a sense amplifier section common to data read of the two-value memory region and data read of the multi-value memory region, for reading data stored in a selected memory cell by comparing a potential of the selected memory cell with a reference potential.
摘要翻译：提供一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括二值存储区域和多值存储器区域，其中该二值存储器区域包括多个存储单元，每个存储器单元存储1位数据，多值存储区包括多个存储2位或更多比特数据的存储单元，以及读出两值存储区域的数据和多值存储器区域的数据读出共同的读出放大器单元，用于读取数据通过将所选择的存储器单元的电位与参考电位进行比较来存储在所选存储单元中。

5. 发明授权

US07088626B2 Bias voltage applying circuit and semiconductor memory device 失效
标题翻译：偏置电压施加电路和半导体存储器件
公开(公告)号：US07088626B2
公开(公告)日：2006-08-08
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译：向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及分别在输出节点和电流供应节点之间调整偏置电压。

6. 发明授权

US06930922B2 Reading circuit, reference circuit, and semiconductor memory device 有权
标题翻译：读取电路，参考电路和半导体存储器件
公开(公告)号：US06930922B2
公开(公告)日：2005-08-16
申请号：US10630568
申请日：2003-07-29
申请人： Yasumichi Mori , Takahiko Yoshimoto , Shinsuke Anzai , Takeshi Nojima
发明人： Yasumichi Mori , Takahiko Yoshimoto , Shinsuke Anzai , Takeshi Nojima
IPC分类号： G11C16/06 , G11C7/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/28
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.
摘要翻译：读取电路，用于从多个存储单元的一个存储单元读取数据，包括多个分割感测电路，每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路，用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。

7. 发明申请

US20050174859A1 Bias voltage applying circuit and semiconductor memory device 失效
标题翻译：偏置电压施加电路和半导体存储器件
公开(公告)号：US20050174859A1
公开(公告)日：2005-08-11
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C16/06 , G11C7/06 , G11C7/12 , G11C16/28 , G11C29/02 , G11C7/00 , G11C7/02
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译：向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及分别在输出节点和电流供应节点之间调整偏置电压。

8. 发明申请

US20110199355A1 DRIVE CIRCUIT AND DISPLAY DEVICE 有权
标题翻译：驱动电路和显示设备
公开(公告)号：US20110199355A1
公开(公告)日：2011-08-18
申请号：US12735930
申请日：2009-02-05
申请人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
发明人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2330/08 , G09G2330/12
摘要： A driving circuit of at least one embodiment includes: m output terminals; m+1 video signal output sections including m+1 output circuits, respectively; a decision section for determining the quality of each of the video signal output sections; and switches for switching connections between the output terminals and the video signal output sections in accordance with a result of determination made by the decision section. When the decision section has determined the ith (i being a natural number of m or less) video signal output section to be defective, the switches connect the jth (j being a natural number of i−1 or less) video signal output section to the jth output terminal and connect the (k+1)th (k being a natural number of i or more to m or less) video signal output section to the kth output terminal. Thus provided is a driving circuit, capable of self-repairing a defective one of the video signal output sections, which has more simplified wires connected to the video signal output sections.
摘要翻译：至少一个实施例的驱动电路包括：m个输出端子; m + 1个视频信号输出部分，分别包括m + 1个输出电路; 确定部分，用于确定每个视频信号输出部分的质量; 以及用于根据决定部分做出的确定的结果来切换输出端子和视频信号输出部分之间的连接。当决定部分确定第i（i个m个或更少的自然数）视频信号输出部分为有缺陷时，该开关将第j个（j是i-1或更小的自然数）视频信号输出部分连接到第j个输出端子，并将第（k + 1）（k为i以上的自然数〜m以下）视频信号输出部连接到第k个输出端子。这样提供了一种驱动电路，其能够自我修复视频信号输出部分中的有缺陷的一个，其具有连接到视频信号输出部分的更简化的线。

9. 发明授权

US08587573B2 Drive circuit and display device 有权
标题翻译：驱动电路和显示设备
公开(公告)号：US08587573B2
公开(公告)日：2013-11-19
申请号：US12735930
申请日：2009-02-05
申请人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
发明人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2330/08 , G09G2330/12
摘要： A driving circuit of at least one embodiment includes: m output terminals; m+1 video signal output sections including m+1 output circuits, respectively; a decision section for determining the quality of each of the video signal output sections; and switches for switching connections between the output terminals and the video signal output sections in accordance with a result of determination made by the decision section. When the decision section has determined the ith (i being a natural number of m or less) video signal output section to be defective, the switches connect the jth (j being a natural number of i−1 or less) video signal output section to the jth output terminal and connect the (k+1)th (k being a natural number of i or more to m or less) video signal output section to the kth output terminal. Thus provided is a driving circuit, capable of self-repairing a defective one of the video signal output sections, which has more simplified wires connected to the video signal output sections.
摘要翻译：至少一个实施例的驱动电路包括：m个输出端子; m + 1个视频信号输出部分分别包括m + 1个输出电路; 确定部分，用于确定每个视频信号输出部分的质量; 以及用于根据决定部分做出的确定的结果来切换输出端子和视频信号输出部分之间的连接。当决定部分确定第i（i个m个或更少的自然数）视频信号输出部分为有缺陷时，该开关将第j个（j是i-1或更小的自然数）视频信号输出部分连接到第j个输出端子，并将第（k + 1）（k为i以上的自然数〜m以下）视频信号输出部连接到第k个输出端子。这样提供了一种驱动电路，其能够自我修复视频信号输出部分中的有缺陷的一个，其具有连接到视频信号输出部分的更简化的线。

10. 发明授权

US09465492B2 Touch panel system and electronic device 有权
标题翻译：触摸屏系统和电子设备
公开(公告)号：US09465492B2
公开(公告)日：2016-10-11
申请号：US14127925
申请日：2012-06-04
申请人： Masayuki Miyamoto , Manabu Yumoto , Shunsuke Nagasawa , Shinichi Yoshida , Kengo Takahama , Masayuki Ehiro , Shinsuke Anzai
发明人： Masayuki Miyamoto , Manabu Yumoto , Shunsuke Nagasawa , Shinichi Yoshida , Kengo Takahama , Masayuki Ehiro , Shinsuke Anzai
IPC分类号： G06F3/044 , G06F3/041
CPC分类号： G06F3/044 , G06F3/0416 , G06F3/0418
摘要： A touch panel system prevents an incorrect operation caused by an unintended contact of an object with a touch panel while suppressing a decline in sensitivity of detection of presence or absence of a touch on the touch panel. The touch panel system includes a touch invalidating section which, in a case where a specific point of a touch panel is continuously touched for a predetermined period of time, invalidates an instruction that is given, in accordance with the touch, to an electronic device including the touch panel.
摘要翻译：触摸面板系统防止由触摸面板上的物体意外接触引起的错误操作，同时抑制触摸面板上触摸的存在或不存在的检测灵敏度的下降。触摸面板系统包括触摸无效部分，其在触摸面板的特定点持续触摸预定时间段的情况下，使根据触摸给出的指令使包括触摸屏。

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