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1. 发明授权

US5852570A Semiconductor memory using select transistors coupled to sub-bitlines from different blocks 失效
标题翻译：使用选择晶体管的半导体存储器，其耦合到来自不同块的子位线
公开(公告)号：US5852570A
公开(公告)日：1998-12-22
申请号：US866498
申请日：1997-05-30
申请人： Yasuhiro Hotta , Takeshi Nojima , Koji Komatsu
发明人： Yasuhiro Hotta , Takeshi Nojima , Koji Komatsu
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C17/12 , H01L21/8246 , H01L27/10 , H01L27/112
CPC分类号： G11C17/126 , H01L27/112
摘要： The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line. The first block includes a first memory transistor having a first electrode, a second electrode and a gate electrode; a first sub-bitline including a part functioning as the first electrode of the first memory transistor; a second sub-bitline including a part functioning as the second electrode of the first memory transistor; and a first word line including a part functioning as the gate electrode of the first memory transistor, while the second block includes: a second memory transistor having a third electrode, a fourth electrode and a gate electrode; a third sub-bitline including a part functioning as the third electrode of the second memory transistor; a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor; and a second word line including a part functioning as the gate electrode of the second memory transistor.
摘要翻译：本发明的半导体存储器件包括：半导体衬底; 第一块与第一块相邻的第二块; 主要位置第一辅助导电区域; 第一选择晶体管; 和第一选择线。第一块包括具有第一电极，第二电极和栅电极的第一存储晶体管; 第一子位线，包括用作第一存储晶体管的第一电极的部分; 第二子位线，包括用作第一存储晶体管的第二电极的部分; 以及第一字线，包括用作第一存储晶体管的栅电极的部分，而第二块包括：具有第三电极，第四电极和栅电极的第二存储晶体管; 第三子位线，包括用作第二存储晶体管的第三电极的部分; 第四子位线，包括用作第二存储晶体管的第四电极的部分; 以及包括用作第二存储晶体管的栅电极的部分的第二字线。

2. 发明授权

US06930922B2 Reading circuit, reference circuit, and semiconductor memory device 有权
标题翻译：读取电路，参考电路和半导体存储器件
公开(公告)号：US06930922B2
公开(公告)日：2005-08-16
申请号：US10630568
申请日：2003-07-29
申请人： Yasumichi Mori , Takahiko Yoshimoto , Shinsuke Anzai , Takeshi Nojima
发明人： Yasumichi Mori , Takahiko Yoshimoto , Shinsuke Anzai , Takeshi Nojima
IPC分类号： G11C16/06 , G11C7/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/28
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.
摘要翻译：读取电路，用于从多个存储单元的一个存储单元读取数据，包括多个分割感测电路，每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路，用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。

3. 发明申请

US20050174859A1 Bias voltage applying circuit and semiconductor memory device 失效
标题翻译：偏置电压施加电路和半导体存储器件
公开(公告)号：US20050174859A1
公开(公告)日：2005-08-11
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C16/06 , G11C7/06 , G11C7/12 , G11C16/28 , G11C29/02 , G11C7/00 , G11C7/02
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译：向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及分别在输出节点和电流供应节点之间调整偏置电压。

4. 发明授权

US07088626B2 Bias voltage applying circuit and semiconductor memory device 失效
标题翻译：偏置电压施加电路和半导体存储器件
公开(公告)号：US07088626B2
公开(公告)日：2006-08-08
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译：向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及分别在输出节点和电流供应节点之间调整偏置电压。

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