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1. 发明申请

US20060022242A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060022242A1
公开(公告)日：2006-02-02
申请号：US11017828
申请日：2004-12-22
申请人： Shinji Sugatani , Koichi Hashimoto , Yoshihiro Takao
发明人： Shinji Sugatani , Koichi Hashimoto , Yoshihiro Takao
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/1087 , H01L21/76229 , H01L27/0629 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.
摘要翻译：半导体器件包括具有沟槽16a和形成在其中的沟槽16b的半导体衬底10; 掩埋在沟槽16a中的器件隔离膜32a，其包括含有氮化硅膜20和氧化硅类绝缘材料的绝缘膜28的衬垫膜; 掩埋在沟槽16b的底部的器件隔离膜32b; 以及形成在第二沟槽16b的上部的侧壁上并且包括作为第一电极的杂质扩散区域40，氧化硅类绝缘膜的电容器电介质膜43和第二电极46的电容器。

2. 发明授权

US07414278B2 Semiconductor device with shallow trench isolation which controls mechanical stresses 有权
标题翻译：具有浅沟槽隔离的半导体器件，其控制机械应力
公开(公告)号：US07414278B2
公开(公告)日：2008-08-19
申请号：US11017828
申请日：2004-12-22
申请人： Shinji Sugatani , Koichi Hashimoto , Yoshihiro Takao
发明人： Shinji Sugatani , Koichi Hashimoto , Yoshihiro Takao
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L21/76229 , H01L27/0629 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.
摘要翻译：半导体器件包括具有沟槽16a和形成在其中的沟槽16b的半导体衬底10; 掩埋在沟槽16a中的器件隔离膜32a，其包括含有氮化硅膜20和氧化硅类绝缘材料的绝缘膜28的衬垫膜; 掩埋在沟槽16b的底部的器件隔离膜32b; 以及形成在第二沟槽16b的上部的侧壁上并且包括作为第一电极的杂质扩散区域40，氧化硅类绝缘膜的电容器电介质膜43和第二电极46的电容器。

3. 发明授权

US07109128B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US07109128B2
公开(公告)日：2006-09-19
申请号：US10866763
申请日：2004-06-15
申请人： Koichi Sugiyama , Yoshihiro Takao , Shinji Sugatani , Daisuke Matsunaga , Takayuki Wada , Tohru Fujita , Hikaru Kokura
发明人： Koichi Sugiyama , Yoshihiro Takao , Shinji Sugatani , Daisuke Matsunaga , Takayuki Wada , Tohru Fujita , Hikaru Kokura
IPC分类号： H01L21/302
CPC分类号： H01L29/665 , H01L21/26586 , H01L21/76897 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/1083 , H01L29/6656 , Y10S257/90
摘要： There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

4. 发明授权

US06800909B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06800909B2
公开(公告)日：2004-10-05
申请号：US10261695
申请日：2002-10-02
申请人： Koichi Sugiyama , Yoshihiro Takao , Shinji Sugatani , Daisuke Matsunaga , Takayuki Wada , Tohru Fujita , Hikaru Kokura
发明人： Koichi Sugiyama , Yoshihiro Takao , Shinji Sugatani , Daisuke Matsunaga , Takayuki Wada , Tohru Fujita , Hikaru Kokura
IPC分类号： H01L2120
CPC分类号： H01L29/665 , H01L21/26586 , H01L21/76897 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/1083 , H01L29/6656 , Y10S257/90
摘要： There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.
摘要翻译：提供了通过栅极绝缘膜形成在一种导电类型的半导体衬底上的栅电极，形成在栅电极的两个侧表面上并且在栅电极和半导体的上表面之间具有间隔的离子注入控制膜衬底，相反导电类型的第一和第二杂质扩散区形成在栅电极两侧的半导体衬底中并且用作源极/漏极，形成在第一和第二杂质扩散之间的栅电极下面的一种导电类型的沟道区具有相反导电类型的区域和一个导电类型的袋区域连接到在栅极电极下方的半导体衬底中的相反导电类型的杂质扩散区域的端部，并且具有比沟道区域高的一种导电类型的杂质浓度。

5. 发明申请

US20130019220A1 METHOD FOR GENERATING WIRING PATTERN DATA 有权
标题翻译：生成接线图数据的方法
公开(公告)号：US20130019220A1
公开(公告)日：2013-01-17
申请号：US13483844
申请日：2012-05-30
申请人： Takashi MARUYAMA , Shinji Sugatani
发明人： Takashi MARUYAMA , Shinji Sugatani
IPC分类号： G06F17/50
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J2237/31761 , H01J2237/31764 , H01J2237/31776
摘要： A method includes connecting in a wiring area a plurality of basic block patterns which include a plurality of track patterns extending to one direction and being disposed at a prescribed pitch in an intersection direction intersecting the one direction to generate a plurality of parallel wiring patterns, each of which includes the track patterns connected together; generating a wiring route running on a track pattern; cutting away a track pattern terminal end, on which no wiring route runs, out of track pattern terminal ends of a track pattern including a route end of the wiring route and an adjacent track pattern connected to a track pattern start end of the track pattern concerned; and generating a wiring pattern data including a block pattern identifier corresponding to a basic block pattern out of the basic block patterns in the wiring area and a layout position of the basic block pattern.
摘要翻译：一种方法包括在布线区域中连接多个基本块图案，所述多个基本块图案包括延伸到一个方向的多个轨迹图案，并且以与所述一个方向交叉的交叉方向以规定间距布置以产生多个平行布线图案，其中包括连接在一起的轨迹图案; 产生在轨道图案上运行的布线路线; 在包括布线路径的路线端的轨迹图案的轨迹图案终端之外，切断没有布线路径的轨道图案终端，以及连接到所述轨道图案的轨道图案开始端的相邻轨道图案 ; 以及生成包括与布线区域中的基本块图案相对应的基本块图案的块图案标识符和基本块图案的布局位置的布线图案数据。

6. 发明授权

US06991996B2 Manufacturing method of semiconductor device and semiconductor chip using SOI substrate, facilitating cleaving 失效
标题翻译：使用SOI衬底的半导体器件和半导体芯片的制造方法，便于切割
公开(公告)号：US06991996B2
公开(公告)日：2006-01-31
申请号：US10634839
申请日：2003-08-06
申请人： Shinji Sugatani , Satoshi Sekino
发明人： Shinji Sugatani , Satoshi Sekino
IPC分类号： H01L21/301 , H01L21/46 , H01L21/78
CPC分类号： H01L21/76254 , H01L2924/0002 , H01L2924/00
摘要： A laminated substrate is formed by laminating a device formation layer made of single crystalline semiconductor on a supporting substrate made of single crystalline semiconductor via an insulating layer with making one direction of a crystallographic axis of the device formation layer be shifted from a corresponding direction of a crystallographic axis of the supporting substrate. Semiconductor devices are formed in the device formation layer within a plurality of areas divided by scribe lines extending to a direction being parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved. The laminated substrate is split into a plurality of chips by cleaving the supporting substrate along the scribe lines. A semiconductor device can easily be split into chips even if a moving direction of carrier and an extending direction of wiring are shifted from an easy-cleaved direction of a crystallographic axis.
摘要翻译：层叠基板通过将由单晶半导体构成的器件形成层通过绝缘层层叠在由单晶半导体构成的支撑基板上而使器件形成层的结晶轴的一个方向从支撑衬底的晶轴。半导体器件形成在多个区域中的器件形成层中，划分为划线延伸到平行于晶体轴方向的方向，其中支撑衬底易于被切割。通过沿着划线切断支撑基板，将层叠基板分割为多个芯片。即使载体的移动方向和布线的延伸方向从结晶轴的易于切割的方向偏移，半导体器件也可以容易地分成芯片。

7. 发明授权

US06900088B2 Semiconductor device and its manufacture method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06900088B2
公开(公告)日：2005-05-31
申请号：US10084367
申请日：2002-02-28
申请人： Ryota Nanjo , Shinji Sugatani , Satoshi Nakai
发明人： Ryota Nanjo , Shinji Sugatani , Satoshi Nakai
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78 , H01L21/8232
CPC分类号： H01L21/823814 , H01L21/823842 , H01L21/82385
摘要： First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity diffusion regions. Spacer films are formed on the side surfaces of the first and second gate electrodes. Second conductivity type impurities are implanted into the first and second regions to form second impurity diffusion regions. After the spacer films are removed, second conductivity type impurities are implanted into the first region to form third impurity diffusion regions. The third activation process is performed so that the gradient of impurity concentration distribution around the third impurity diffusion region becomes steeper than the gradient of impurity concentration distribution around the first impurity diffusion region.
摘要翻译：第一和第二栅电极形成在半导体衬底的第一和第二区上。将第二导电型杂质注入到第二区域中以形成第一杂质扩散区。间隔膜形成在第一和第二栅电极的侧表面上。将第二导电型杂质注入第一和第二区域以形成第二杂质扩散区。在去除间隔膜之后，将第二导电型杂质注入第一区域以形成第三杂质扩散区。执行第三激活处理，使得第三杂质扩散区周围的杂质浓度分布的梯度比第一杂质扩散区周围的杂质浓度分布的梯度变得更陡。

8. 发明授权

US06277718B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06277718B1
公开(公告)日：2001-08-21
申请号：US09047522
申请日：1998-03-25
申请人： Hiroyuki Naganuma , Shinji Sugatani
发明人： Hiroyuki Naganuma , Shinji Sugatani
IPC分类号： H01L213205
CPC分类号： H01L21/28211 , H01L21/28176 , H01L21/31629 , Y10S438/91
摘要： The method for fabricating a semiconductor device comprises an insulation film forming step of forming an insulation film 12 on a semiconductor substrate 10, a semiconductor layer forming step of forming a semiconductor layer 14 on the insulation film 12, and an impurity implanting step of implanting an impurity containing hydrogen into the semiconductor layer 14, the method being characterized by further comprising a fluorine implanting step of implanting fluorine in at least the insulation film 12. The dangling bonds of the insulation film can be bonded with the fluorine, whereby the fluorine, which has higher bonding energy with respect to silicon of the insulation film than hydrogen, is never dissociated from the silicon of the insulation film in the following heat treatments, BT stress test, etc. Accordingly, an interface state density in the interface between the insulation film and the semiconductor substrate can be depressed low, and a fixed charge in the insulation film can be depressed small. The semiconductor device and the method for fabricating the same can be reliable. The fluorine ion dose is suitably set to thereby prevent the insulation film from thickening. The method for fabricating a semiconductor device having good electric characteristics can be provided.
摘要翻译：半导体器件的制造方法包括在半导体衬底10上形成绝缘膜12的绝缘膜形成步骤，在绝缘膜12上形成半导体层14的半导体层形成步骤以及植入含有氢的杂质进入半导体层14，该方法的特征在于还包括在至少绝缘膜12中注入氟的氟注入步骤。绝缘膜的悬挂键可以与氟键合，由此氟相对于绝缘膜的硅相对于氢具有更高的结合能，在以下热处理，BT应力测试等中绝不会从绝缘膜的硅离解。因此，绝缘膜之间的界面中的界面态密度并且半导体衬底可以被低压，并且可以在绝缘膜中固定电荷郁闷的小。半导体器件及其制造方法可以是可靠的。适当设定氟离子剂量，防止绝缘膜变厚。可以提供具有良好电特性的半导体器件的制造方法。

9. 发明授权

US06649965B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06649965B2
公开(公告)日：2003-11-18
申请号：US10091507
申请日：2002-03-07
申请人： Kazuhiko Takada , Shinji Sugatani
发明人： Kazuhiko Takada , Shinji Sugatani
IPC分类号： H01L2976
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： There are provided the steps of forming a tunnel insulating film on a semiconductor substrate, forming a first semiconductor film constituting a lower portion of a floating gate on the tunnel insulating film, forming device isolation recesses by etching device isolation regions on the first semiconductor film, the tunnel insulating film, and the semiconductor substrate, forming an device isolation insulating film in the device isolation recesses and on the first semiconductor film, removing the device isolation insulating film from an upper surface of the first semiconductor film and thinning the device isolation insulating film on the device isolation recesses, growing selectively a second semiconductor film serving as an upper portion of the floating gate on the first semiconductor film and growing the second semiconductor film on the device isolation insulating film to extend in the lateral direction, forming a dielectric film on the floating gate, and forming a conductive film serving as a control gate on the dielectric film.

10. 发明申请

US20090327164A1 LOAD DISTRIBUTING METHOD, COMPUTER PRODUCT, AND LOAD DISTRIBUTING APPARATUS 审中-公开
标题翻译：负载分配方法，计算机产品和负载分配设备
公开(公告)号：US20090327164A1
公开(公告)日：2009-12-31
申请号：US12553201
申请日：2009-09-03
申请人： Hitoshi Saito , Takuya Honda , Masahiro Sueda , Shinji Sugatani
发明人： Hitoshi Saito , Takuya Honda , Masahiro Sueda , Shinji Sugatani
IPC分类号： G06Q20/00 , G06F9/50 , G06F15/16
CPC分类号： G06Q10/00 , G06F9/5027 , G06F9/5072 , G06Q30/00 , G06Q30/0283
摘要： A load distributing method includes receiving information concerning resources of a terminal device from the terminal device in a grid on a network of a grid computing system; extracting, from a computation data group related to grid computing and based on the received information concerning resources, computation data corresponding to the resources; and distributing to the terminal device, the extracted computation data together with content reproducible during processing of the computation data.
摘要翻译：负载分配方法包括从网格计算系统的网络上的网格中的终端装置接收有关终端装置的资源的信息; 从与网格计算相关的计算数据组中提取与所述资源相关的接收信息，对应于所述资源的计算数据; 并且将所提取的计算数据与在计算数据的处理期间可再现的内容一起分发给终端设备。

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