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1. 发明授权

US06365443B1 Method of manufacturing a semiconductor device having data pads formed in scribed area 有权
标题翻译：制造具有形成在划刻区域中的数据焊盘的半导体器件的方法
公开(公告)号：US06365443B1
公开(公告)日：2002-04-02
申请号：US09538231
申请日：2000-03-30
申请人： Shingo Hagiwara , Amane Inoue , Eiichi Nagai , Masaji Inami , Tohru Takeshima , Kouichi Noro , Hideaki Suzuki
发明人： Shingo Hagiwara , Amane Inoue , Eiichi Nagai , Masaji Inami , Tohru Takeshima , Kouichi Noro , Hideaki Suzuki
IPC分类号： H01L2182
CPC分类号： H01L27/10 , H01L22/32 , H01L24/06 , H01L27/112 , H01L2224/05554 , H01L2224/4943 , H01L2924/00011 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electrically connecting the pads with the memory areas. The pads are formed within the scribe areas. After data has been written into the memory areas through the pads, the semiconductor wafer is cut along the scribe areas, thereby obtaining semiconductor chips. At the time of this cutting, the pads or the lead wires are cut.
摘要翻译：在半导体晶片上形成用于存储存储区域的芯片区域，用于切割半导体晶片的划片区域，用于从外部提供电信号的焊盘，以将数据写入存储区域，以及用于将焊盘电连接的引线与用于内存区域。垫片形成在划线区域内。在通过焊盘将数据写入存储区域之后，沿划刻区域切割半导体晶片，从而获得半导体芯片。在切割时，切割垫或引线。

2. 发明授权

US07688182B2 RFID system and RFID chip equipped with sensor function 有权
标题翻译： RFID系统和RFID芯片配备传感器功能
公开(公告)号：US07688182B2
公开(公告)日：2010-03-30
申请号：US11360601
申请日：2006-02-24
申请人： Eiichi Nagai
发明人： Eiichi Nagai
IPC分类号： H04Q5/22 , B60C23/02 , G01S13/08
CPC分类号： G06K19/0723 , G06K19/0717
摘要： An integrated circuit chip includes a rectifier circuit configured to convert an alternating voltage supplied from an antenna into a direct-current voltage, a nonvolatile memory coupled to the rectifier circuit to operate by use of the direct-current voltage, a sensor circuit coupled to the rectifier circuit to operate by use of the direct-current voltage to collect measurement data, and a logic circuit configured to control the nonvolatile memory and the sensor circuit such that an access operation of the nonvolatile memory and a data collecting operation of the sensor circuit are not performed concurrently.
摘要翻译：集成电路芯片包括：整流电路，被配置为将从天线提供的交流电压转换成直流电压;非易失性存储器，其耦合到整流器电路以通过使用直流电压进行操作;传感器电路，整流电路通过使用直流电压进行操作以收集测量数据;以及逻辑电路，被配置为控制非易失性存储器和传感器电路，使得非易失性存储器的访问操作和传感器电路的数据收集操作是不同时执行。

3. 发明授权

US5835790A Apparatus for data transfer capable of pipeline processing by cascading processing circuits without relying on external clock with an output circuit relying on external clock 失效
标题翻译：用于通过级联处理电路进行流水线处理的数据传输装置，而不依赖于具有依赖于外部时钟的输出电路的外部时钟
公开(公告)号：US5835790A
公开(公告)日：1998-11-10
申请号：US526278
申请日：1995-09-11
申请人： Eiichi Nagai , Yoshihiro Takemae , Hirohiko Mochizuki , Yukihiro Nomura
发明人： Eiichi Nagai , Yoshihiro Takemae , Hirohiko Mochizuki , Yukihiro Nomura
IPC分类号： G06F9/38 , G06F12/00 , G11C7/10 , G06F3/00
CPC分类号： G11C7/1051 , G06F9/3869 , G11C7/1039
摘要： A data transfer apparatus is disclosed which has a first, a second, and a third pipeline processing circuits disposed in cascade connection. The first and the second pipeline processing circuits are each provided with an arbitrary signal processing circuit, a switch element for controlling the introduction of data into the signal processing circuit, and a switch control circuit for turning on the switch element on detecting completion of the transfer of data from the signal processing circuit to a pipeline processing circuit in the subsequent stage. The third pipeline processing circuit is provided with an output circuit and a switch element for introducing data transferred from the second pipeline processing circuit into the output circuit as synchronized with an external clock signal. Between the first and the second pipeline processing circuit, therefore, data can be transferred with a timing conforming to the timing of the operation of the signal processing circuit without being synchronized with an external clock signal. In the output circuit, data can be issued as synchronized with an external clock signal. Thus, a signal of a very high frequency can be selected as a clock signal for setting the timing of the whole of a system incorporating the data transfer apparatus therein.
摘要翻译：公开了一种数据传送装置，其具有级联连接设置的第一，第二和第三流水线处理电路。第一和第二流水线处理电路分别设置有任意的信号处理电路，用于控制将数据引入信号处理电路的开关元件，以及用于在检测到转印完成时接通开关元件的开关控制电路的数据从信号处理电路到后续阶段的流水线处理电路。第三流水线处理电路设置有与外部时钟信号同步地将从第二流水线处理电路传送的数据引入输出电路的输出电路和开关元件。因此，在第一和第二流水线处理电路之间，可以以与外部时钟信号同步的信号处理电路的操作的定时的定时来传送数据。在输出电路中，数据可以与外部时钟信号同步发出。因此，可以选择非常高频率的信号作为用于设置其中包含数据传送装置的系统整体的定时的时钟信号。

4. 发明授权

US06246616B1 Memory device having redundancy cells 有权
标题翻译：具有冗余单元的存储器件
公开(公告)号：US06246616B1
公开(公告)日：2001-06-12
申请号：US09487878
申请日：2000-01-20
申请人： Eiichi Nagai , Chikai Ono
发明人： Eiichi Nagai , Chikai Ono
IPC分类号： G11C700
CPC分类号： G11C29/789 , G11C11/22 , G11C29/808 , G11C29/846
摘要： The present invention relates to a memory device, such as a FeRAM, of which redundancy structure is simplified. In the present invention, a redundancy file memory for recording a replacing information indicating the defective cell to be replaced into a redundancy cell is formed by a memory cell having the same structure as a normal memory cell, so that it is capable to access to a redundancy file memory at the same time when accessing to a normal memory cell. Then, the replacing information recorded in the redundancy file memory is concurrently read out when accessing to the normal memory cell, and the defective cell is replaced into a redundancy cell according to the replacing information.
摘要翻译：本发明涉及冗余结构简化的诸如FeRAM的存储器件。在本发明中，通过具有与正常存储单元相同结构的存储单元形成用于将表示要替代的缺陷单元的替换信息记录到冗余单元中的冗余文件存储器，从而能够访问冗余文件存储器在访问正常存储器单元时同时进行。然后，当访问正常存储器单元时，同时读出记录在冗余文件存储器中的替换信息，并且根据替换信息将缺陷单元替换为冗余单元。

5. 发明授权

US4890164A Image sensor having charge storage regions 失效
标题翻译：具有电荷存储区域的图像传感器
公开(公告)号：US4890164A
公开(公告)日：1989-12-26
申请号：US253646
申请日：1988-10-05
申请人： Akira Takei , Teruyuki Nabeta , Tetsuo Nishikawa , Eiichi Nagai
发明人： Akira Takei , Teruyuki Nabeta , Tetsuo Nishikawa , Eiichi Nagai
IPC分类号： H01L21/339 , H01L27/148 , H01L29/762 , H04N1/028 , H04N5/335 , H04N5/341 , H04N5/369 , H04N5/372 , H04N5/374 , H04N5/378
CPC分类号： H01L27/14825 , H04N3/155
摘要： An image sensor includes a plurality of potential monitoring transistors connected to respective floating electrodes for separately monitoring changes in potential of the respective floating electrodes. In addition, the image sensor includes an output circuit for producing an output signal which varies in accordance with one of the monitored potentials which is one of the highest potential and the lowest potential.

6. 发明申请

US20070096880A1 RFID system and RFID chip equipped with sensor function 有权
标题翻译： RFID系统和RFID芯片配备传感器功能
公开(公告)号：US20070096880A1
公开(公告)日：2007-05-03
申请号：US11360601
申请日：2006-02-24
申请人： Eiichi Nagai
发明人： Eiichi Nagai
IPC分类号： H04Q5/22
CPC分类号： G06K19/0723 , G06K19/0717
摘要： An integrated circuit chip includes a rectifier circuit configured to convert an alternating voltage supplied from an antenna into a direct-current voltage, a nonvolatile memory coupled to the rectifier circuit to operate by use of the direct-current voltage, a sensor circuit coupled to the rectifier circuit to operate by use of the direct-current voltage to collect measurement data, and a logic circuit configured to control the nonvolatile memory and the sensor circuit such that an access operation of the nonvolatile memory and a data collecting operation of the sensor circuit are not performed concurrently.
摘要翻译：集成电路芯片包括：整流电路，被配置为将从天线提供的交流电压转换成直流电压;非易失性存储器，其耦合到整流器电路以通过使用直流电压进行操作;传感器电路，整流电路通过使用直流电压进行操作以收集测量数据;以及逻辑电路，被配置为控制非易失性存储器和传感器电路，使得非易失性存储器的访问操作和传感器电路的数据收集操作是不同时执行。

7. 发明授权

US5448528A Synchronous DRAM having initial mode setting circuit 失效
标题翻译：具有初始模式设定电路的同步DRAM
公开(公告)号：US5448528A
公开(公告)日：1995-09-05
申请号：US307420
申请日：1994-09-19
申请人： Eiichi Nagai
发明人： Eiichi Nagai
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/4096 , G11C13/00
CPC分类号： G11C11/4096 , G11C7/1045 , G11C7/1072
摘要： The initial mode setting circuit 30 has a circuit 31 for generating a reset pulse RST after detecting that the power source voltage VCC has reached a specified value when the power source voltage VCC starts up, and fuses 32 to 37, each one end of which is commonly connected to the output end of the reset signal generating circuit 31 and the other ends of which are connected to one of either the set input end S or the reset input end R of the flip flops 11 to 13. The fuses 32 to 37 are melted and cut off electrically or with a laser.
摘要翻译：初始模式设置电路30具有电路31，用于在电源电压VCC启动时检测到电源电压VCC已经达到指定值后产生复位脉冲RST，并且熔断器32至37的每一端为通常连接到复位信号发生电路31的输出端，其另一端连接到触发器11至13的设定输入端S或复位输入端R之一。保险丝32至37是熔化并用激光切断。

8. 发明授权

US5221852A Charge coupled device and method of producing the same 失效
标题翻译：电荷耦合器件及其制造方法
公开(公告)号：US5221852A
公开(公告)日：1993-06-22
申请号：US829189
申请日：1992-02-03
申请人： Eiichi Nagai , Tetsuo Nishikawa
发明人： Eiichi Nagai , Tetsuo Nishikawa
IPC分类号： H01L29/762 , H01L21/339 , H01L27/148 , H01L29/768 , H04N5/335 , H04N5/341 , H04N5/357 , H04N5/372
CPC分类号： H01L29/76833 , H01L27/14831
摘要： A charge coupled device (CCD) has a charge storage region and a potential barrier region. The CCD includes a first layer made of a first conductivity type semiconductor, a second layer made of a second conductivity type semiconductor and provided on the first layer, where the first and second conductivity types are mutually opposite types selected from n-type and p-type semiconductors, a third layer made of a first conductivity type semiconductor, impurity diffusion regions provided in at least a surface part of the third layer and having an impurity density higher than that of the third layer, a first gate electrode provided on the third layer between two mutually adjacent impurity diffusion regions, and a second gate electrode provided on each impurity diffusion region of the third layer. The impurity diffusion region forms the charge storage region of the CCD and the third layer between the two mutually adjacent impurity diffusion regions forms the potential barrier region of the CCD.
摘要翻译：电荷耦合器件（CCD）具有电荷存储区域和势垒区域。 CCD包括由第一导电类型半导体制成的第一层，由第二导电类型半导体制成的第二层，设置在第一层上，其中第一和第二导电类型是相互相反的类型，选自n型和p-型，型半导体，由第一导电型半导体制成的第三层，在第三层的至少表面部分设置的杂质浓度高于第三层的杂质浓度的杂质扩散区，设置在第三层上的第一栅电极在两个相互相邻的杂质扩散区之间，以及设置在第三层的每个杂质扩散区上的第二栅电极。杂质扩散区域形成CCD的电荷存储区域，并且两个相互相邻的杂质扩散区域之间的第三层形成CCD的势垒区域。

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