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1. 发明授权

US06365443B1 Method of manufacturing a semiconductor device having data pads formed in scribed area 有权
标题翻译：制造具有形成在划刻区域中的数据焊盘的半导体器件的方法
公开(公告)号：US06365443B1
公开(公告)日：2002-04-02
申请号：US09538231
申请日：2000-03-30
申请人： Shingo Hagiwara , Amane Inoue , Eiichi Nagai , Masaji Inami , Tohru Takeshima , Kouichi Noro , Hideaki Suzuki
发明人： Shingo Hagiwara , Amane Inoue , Eiichi Nagai , Masaji Inami , Tohru Takeshima , Kouichi Noro , Hideaki Suzuki
IPC分类号： H01L2182
CPC分类号： H01L27/10 , H01L22/32 , H01L24/06 , H01L27/112 , H01L2224/05554 , H01L2224/4943 , H01L2924/00011 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electrically connecting the pads with the memory areas. The pads are formed within the scribe areas. After data has been written into the memory areas through the pads, the semiconductor wafer is cut along the scribe areas, thereby obtaining semiconductor chips. At the time of this cutting, the pads or the lead wires are cut.
摘要翻译：在半导体晶片上形成用于存储存储区域的芯片区域，用于切割半导体晶片的划片区域，用于从外部提供电信号的焊盘，以将数据写入存储区域，以及用于将焊盘电连接的引线与用于内存区域。垫片形成在划线区域内。在通过焊盘将数据写入存储区域之后，沿划刻区域切割半导体晶片，从而获得半导体芯片。在切割时，切割垫或引线。

2. 发明授权

US06288930B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06288930B1
公开(公告)日：2001-09-11
申请号：US09578913
申请日：2000-05-26
申请人： Tohru Takeshima , Kouichi Noro
发明人： Tohru Takeshima , Kouichi Noro
IPC分类号： G11C1124
CPC分类号： G11C11/22
摘要： A semiconductor memory device has a first ferroelectric memory cell in which data is written after the device is mounted on a board, and a second ferroelectric memory cell whose capacitance is larger than that of the first ferroelectric memory cell. This second ferroelectric memory cell is utilized as a memory cell in which cipher or the like are written in the fabrication process. The second ferroelectric memory cell is formed with a combination of a plurality of the first ferroelectric memory cells. In order to realize the second ferroelectric memory cell, word lines or plate lines corresponding to a plurality memory-cell rows may be short-circuited. Alternatively, bit lines corresponding to a plurality memory-cell columns may be short-circuited.
摘要翻译：半导体存储器件具有第一铁电存储单元，其中在将器件安装在板上之后写入数据，以及第二铁电存储单元，其电容大于第一铁电存储单元的电容。该第二铁电存储单元被用作在制造过程中写入密码等的存储单元。第二铁电存储单元由多个第一铁电存储单元的组合形成。为了实现第二铁电存储单元，对应于多个存储单元行的字线或板线可能短路。或者，对应于多个存储单元列的位线可能短路。

3. 发明授权

US06922683B2 CTI server and program recording medium 失效
标题翻译： CTI服务器和程序记录介质
公开(公告)号：US06922683B2
公开(公告)日：2005-07-26
申请号：US09922699
申请日：2001-08-07
申请人： Chika Kayaba , Kouichi Noro
发明人： Chika Kayaba , Kouichi Noro
IPC分类号： G06E1/00 , G06F3/00 , G06F3/048 , G06F17/00 , G06N5/02 , G06Q50/00 , G06Q50/30 , G06Q50/32 , H04M3/42 , H04M3/51 , H04M7/00
CPC分类号： H04M3/5175 , G06Q30/02 , H04M3/42042 , H04M3/5183 , H04M7/0012 , H04M2201/38
摘要： A CTI server receives calls from telephone terminals. The CTI server includes an analysis unit, an icon creating unit, and an icon display control unit. The analysis unit analyzes conditions for a call from a telephone terminal to generate parameter which represents the presumed psychological state of a customer using the telephone terminal. The icon creating unit creates an icon for visually displaying the presumed psychological state of the customer on the basis of the parameters. The icon display control unit for displaying the presumed psychological state of the customer using the icon.
摘要翻译： CTI服务器从电话终端接收呼叫。 CTI服务器包括分析单元，图标创建单元和图标显示控制单元。分析单元分析来自电话终端的呼叫的条件，以产生表示使用电话终端的客户的假设心理状态的参数。图标创建单元基于参数创建用于可视地显示顾客的假设心理状态的图标。图标显示控制单元，用于使用该图标来显示顾客的假想心理状态。

4. 发明授权

US06330180B2 Semiconductor memory device with reduced power consumption and with reduced test time 有权
标题翻译：半导体存储器件，功耗降低，测试时间缩短
公开(公告)号：US06330180B2
公开(公告)日：2001-12-11
申请号：US09770286
申请日：2001-01-29
申请人： Kouichi Noro , Yoshioka Hiroshi
发明人： Kouichi Noro , Yoshioka Hiroshi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the activated one of the global plate lines to one of the local plate lines in the selected one of the units so as to achieve the same potential therebetween.
摘要翻译：半导体存储器件包括铁电存储器单元，连接在存储器单元的第一节点和数据传输线之间的单元晶体管，存储单元和单元晶体管被分组成单元，每个单元对应于一个或多个列地址，全局字线，其被响应于相应行地址的选择被激活，全局板行，其中之一响应于对应的行地址的选择被激活，每个本地字线被提供并专用于相应的一个单元并且连接到单元晶体管的栅极，本地板线，其中每个板被提供并专用于相应的一个单元，并且连接到存储单元的第二节点;以及单元开关电路，其将将一个全局字线激活到所选择的一个单元中的一个本地字线，以在其间实现相同的电位，并且电将所激活的一个全局板线与所选择的一个单元中的一个局部板线相连，以在其间实现相同的电位。

5. 发明授权

US06912175B2 Semiconductor memory and method of controlling the same 有权
标题翻译：半导体存储器及其控制方法
公开(公告)号：US06912175B2
公开(公告)日：2005-06-28
申请号：US10636708
申请日：2003-08-08
申请人： Kouichi Noro
发明人： Kouichi Noro
IPC分类号： G11C11/22 , G11C8/00
CPC分类号： G11C11/22
摘要： Each of a plurality of memory cells includes one ferroelectric capacitor having one terminal connected to a bit line. A plurality of decoder circuits are arranged on each of the plurality of memory cells, and connected to the other terminal of the ferroelectric capacitor forming the memory cells via a plurality of word lines. These plurality of decoder circuits control the word lines to one of high level, low level, and a floating state, thereby writing data in the memory cells or reading out data from the memory cells.
摘要翻译：多个存储单元中的每一个包括一个铁电电容器，其一端连接到位线。多个解码器电路被布置在多个存储单元中的每一个上，并且经由多个字线连接到形成存储单元的铁电电容器的另一个端子。这些多个解码器电路将字线控制为高电平，低电平和浮置状态之一，从而将数据写入存储器单元或从存储器单元读出数据。

6. 发明授权

US06795331B2 Ferroelectric memory wherein bit line capacitance can be maximized 失效
标题翻译：铁电存储器，其中位线电容可以最大化
公开(公告)号：US06795331B2
公开(公告)日：2004-09-21
申请号：US10334060
申请日：2002-12-31
申请人： Kouichi Noro
发明人： Kouichi Noro
IPC分类号： G11C1112
CPC分类号： G11C11/22
摘要： In a ferroelectric memory, there are provided a plurality of word lines, a plurality of bit lines crossing there-with, a plurality of memory cells having ferroelectric capacitors arranged at the positions of these crossovers and a plurality of correction capacitors connectable with the bit lines. At least some of the plurality of correction capacitors are connected with a bit line so as to be capable of increasing bit line capacitance by a prescribed amount.
摘要翻译：在铁电存储器中，提供了多条字线，多条与其相交的位线，多个具有布置在这些交叉位置的铁电电容器的存储单元和可与位线连接的多个校正电容器。多个校正电容器中的至少一些与位线连接，以便能够将位线电容增加预定量。

7. 发明授权

US06560138B2 Semiconductor memory device with reduced power consumption and with reduced test time 有权
公开(公告)号：US06560138B2
公开(公告)日：2003-05-06
申请号：US09982768
申请日：2001-10-22
申请人： Kouichi Noro , Yoshioka Hiroshi
发明人： Kouichi Noro , Yoshioka Hiroshi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the activated one of the global plate lines to one of the local plate lines in the selected one of the units so as to achieve the same potential therebetween.

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