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1. 发明授权

US4636831A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4636831A
公开(公告)日：1987-01-13
申请号：US517256
申请日：1983-07-26
申请人： Chikai Ono , Yoshinori Okajima
发明人： Chikai Ono , Yoshinori Okajima
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L27/08 , H01L27/10 , H01L27/118
CPC分类号： H01L27/0802
摘要： A semiconductor device including a plurality of resistors. All the resistors are contained in circuit block regions which are arranged successively in a first direction. Each of the resistors is extended in the first direction. All of the resistors are set up in the form of a plurality of stages arranged in a second direction perpendicular to the first direction and in parallel with each other.
摘要翻译：一种包括多个电阻器的半导体器件。所有电阻器都包含在沿第一方向依次布置的电路块区域中。每个电阻器沿第一方向延伸。所有的电阻器都是以垂直于第一方向并且彼此平行的第二方向布置的多个级的形式设置的。

2. 发明授权

US4231108A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4231108A
公开(公告)日：1980-10-28
申请号：US48256
申请日：1979-06-13
申请人： Masao Suzuki , Toshio Hayashi , Kuniyasu Kawarada , Kazuhiro Toyoda , Chikai Ono
发明人： Masao Suzuki , Toshio Hayashi , Kuniyasu Kawarada , Kazuhiro Toyoda , Chikai Ono
IPC分类号： G11C5/06 , G11C11/411 , G11C11/415 , H01L21/3205 , H01L21/822 , H01L21/8226 , H01L23/52 , H01L27/04 , H01L27/082 , H01L27/102 , G11C11/40
CPC分类号： H01L27/1025 , G11C11/4113 , G11C11/415 , G11C5/063
摘要： An improved semiconductor integrated circuit device having a memory cell array formed of integrated injection logic memory cells. The semiconductor integrated circuit according to the present invention includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions, one of the word lines being formed by a semiconductor bulk, current sources provided at least at both ends of the word lines or the bit lines.
摘要翻译：一种改进的半导体集成电路器件，具有由集成注入逻辑存储单元形成的存储单元阵列。根据本发明的半导体集成电路包括以矩阵形式布置的集成注入逻辑存储单元，连接到以行或列方向布置的存储单元的字线和位线，其中一条字线由半导体本体，至少在字线或位线的两端提供电流源。

3. 发明授权

US5138199A Level conversion circuit for converting ECL-level signal into TTL-level signal 失效
标题翻译：将电平信号转换为TTL电平信号的电平转换电路
公开(公告)号：US5138199A
公开(公告)日：1992-08-11
申请号：US524467
申请日：1990-05-17
申请人： Michiyuki Hirata , Chikai Ono , Osamu Nomura , Toru Fukui , Susumu Terawaki
发明人： Michiyuki Hirata , Chikai Ono , Osamu Nomura , Toru Fukui , Susumu Terawaki
IPC分类号： H03K19/094 , H03K19/003 , H03K19/013 , H03K19/0175 , H03K19/0944 , H03K19/0952
CPC分类号： H03K19/09448 , H03K19/00307 , H03K19/013 , H03K19/017527
摘要： A level conversion circuit includes a level converter and a buffer gate circuit. A level converter includes two pairs of P-channel MOS transistors. A first input signal is supplied to one of the pair of P-channel MOS transistors and a second input signal is supplied to one of the other pair of P-channel MOS transistors. Each of the first and second input signals are complementary ECL-level signals. The buffer gate circuit includes two BiCMOS circuits. A first output signal from one of the pairs of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in one of the BiCMOS circuits. A second output signal from the other pair of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in the other BiCMOS circuit. The first input signal is supplied directly to a gate of a P-channel MOS transistor provided in one the BiCMOS circuits. The second input signal is supplied directly to a gate of a P-channel MOS transistor provided in the other BiCMOS circuit. A first TTL-level output signal is output from one of the circuits, and a second TTL-level output signal is output from the other BiCMOS circuit.

4. 发明授权

US4815037A Bipolar type static memory cell 失效
标题翻译：双极型静电记忆体
公开(公告)号：US4815037A
公开(公告)日：1989-03-21
申请号：US549003
申请日：1983-11-03
申请人： Kazuhiro Toyoda , Chikai Ono
发明人： Kazuhiro Toyoda , Chikai Ono
IPC分类号： G11C11/411 , H01L21/331 , H01L21/74 , H01L21/8222 , H01L21/8229 , H01L27/02 , H01L27/06 , H01L27/07 , H01L27/102 , H01L29/73 , H01L27/04 , G11C11/40 , H03K19/091
CPC分类号： G11C11/4116 , G11C11/4113 , H01L21/74 , H01L27/0233 , H01L27/0755 , H01L27/1025
摘要： A bipolar type static memory cell comprising two cross connected circuits, each of the circuits including a transistor and a load element is disclosed. An N-type epitaxial layer, grown on an N.sup.+ -type buried layer, is used as a collector region of the transistor, and a P-type layer formed in the N-type epitaxial layer and an N.sup.+ -type layer formed in the P-type layer are used as a base region and an emitter region of the transistor. A P-type diffusion layer is formed in the N-type epitaxial layer from the surface of the epitaxial layer to reach and contact the buried layer. The structure results in the memory cell parasitic diodes being effectively eliminated from the cell together with the unwanted charge storage effects of the diodes.
摘要翻译：公开了一种包括两个交叉连接电路的双极型静态存储单元，每个电路包括晶体管和负载元件。使用在N +型掩埋层上生长的N型外延层作为晶体管的集电极区域，形成在N型外延层中的P型层和形成在P型层中的N +型层型层用作晶体管的基极区域和发射极区域。从外延层的表面在N型外延层中形成P型扩散层，以到达并接触埋层。该结构导致存储单元寄生二极管与二极管的不需要的电荷存储效应一起被有效地从单元中消除。

5. 发明授权

US4419745A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4419745A
公开(公告)日：1983-12-06
申请号：US179793
申请日：1980-08-20
申请人： Kazuhiro Toyoda , Chikai Ono
发明人： Kazuhiro Toyoda , Chikai Ono
IPC分类号： G11C11/41 , G11C5/06 , G11C11/411 , G11C11/414 , H01L21/822 , H01L21/8226 , H01L21/8229 , H01L27/04 , H01L27/082 , H01L27/102 , H01L29/78 , H03K19/091 , G11C11/40
CPC分类号： G11C11/4113 , G11C5/063 , H01L27/1025
摘要： An improvement of a semiconductor integrated circuit device of a memory cell array which is formed by integrated injection logic memory cells. The semiconductor integrated circuit includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions and which are formed by a semiconductor bulk. A current source is provided around the middle portion of each word line.
摘要翻译：由集成注入逻辑存储单元形成的存储单元阵列的半导体集成电路器件的改进。半导体集成电路包括以矩阵形式布置的集成注入逻辑存储单元，字线和位线，其连接到以行或列方向排列并由半导体本体形成的存储单元。在每个字线的中间部分周围设置电流源。

6. 发明授权

US4374431A I.sup.2 L Semiconductor memory circuit device 失效
标题翻译： I2L半导体存储器电路器件
公开(公告)号：US4374431A
公开(公告)日：1983-02-15
申请号：US210678
申请日：1980-11-26
申请人： Chikai Ono , Kazuhiro Toyoda
发明人： Chikai Ono , Kazuhiro Toyoda
IPC分类号： G11C5/06 , G11C11/411 , G11C11/415 , G11C11/416 , H01L27/02 , H03K3/288 , G11C11/40
CPC分类号： H03K3/288 , G11C11/4113 , G11C11/4116 , G11C11/415 , G11C11/416 , G11C5/063 , H01L27/0233
摘要： A semiconductor memory circuit device is disclosed. The semiconductor memory circuit device is conventionally comprised of a plurality of memory-cell arrays. Each of the memory-cell arrays is conventionally provided with a plurality of IIL memory cells, a pair of positive word line and negative work line and further a plurality of bit lines. In the semiconductor memory circuit device, at least one means for discharging electric charges is newly incorporated with each negative word line. Said means becomes active only when the corresponding memory-cell array changes from selection status to non-selection status.
摘要翻译：公开了一种半导体存储器电路器件。半导体存储器电路器件通常由多个存储单元阵列组成。每个存储单元阵列通常设置有多个IIL存储单元，一对正字线和负工作线以及多个位线。在半导体存储器电路装置中，每个负字线新引入至少一个用于放电电荷的装置。所述装置仅在对应的存储单元阵列从选择状态改变为非选择状态时变为有效。

7. 发明授权

US4228525A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4228525A
公开(公告)日：1980-10-14
申请号：US38016
申请日：1979-05-11
申请人： Kuniyasu Kawarada , Masao Suzuki , Chikai Ono , Kazuhiro Toyoda
发明人： Kuniyasu Kawarada , Masao Suzuki , Chikai Ono , Kazuhiro Toyoda
IPC分类号： G11C5/06 , G11C11/411 , H01L27/102 , G11C11/40
CPC分类号： H01L27/1025 , G11C11/4113 , G11C5/063
摘要： A semiconductor integrated circuit device has an array of memory cells formed by integrated injection logic. A desired number of dummy cells are provided at both ends of each line of the array, so that a write current, which flows when the memory cell near the dummy cell is selected, is shunted by the dummy cell, thereby the currents which flow in the memory cells in the line of the memory array are equalized.
摘要翻译：半导体集成电路器件具有由集成注入逻辑形成的存储单元阵列。在阵列的每一行的两端设置所需数量的虚设单元，从而在虚拟单元附近的存储单元被选择时流入的写入电流被虚设的单元分流，从而流入存储器阵列的行中的存储器单元被均衡。

8. 发明授权

US06229728B1 Ferroelectric memory and method of testing the same 有权
标题翻译：铁电存储器和测试方法相同
公开(公告)号：US06229728B1
公开(公告)日：2001-05-08
申请号：US09296544
申请日：1999-04-22
申请人： Chikai Ono , Hirokazu Yamazaki
发明人： Chikai Ono , Hirokazu Yamazaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.
摘要翻译：铁电存储器包括存储器单元，存储单元连接到的一对位线，以及控制电路，其将从一个存储单元读取的数据输出到对应于一对位线之一的参考单元，另一个位线对。

9. 发明授权

US4231109A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4231109A
公开(公告)日：1980-10-28
申请号：US53274
申请日：1979-06-29
申请人： Chikai Ono , Kazuhiro Toyoda
发明人： Chikai Ono , Kazuhiro Toyoda
IPC分类号： G11C5/06 , G11C11/411 , G11C11/415 , H01L27/102 , H03K3/288 , G11C11/40
CPC分类号： H03K3/288 , G11C11/4113 , G11C11/415 , G11C5/063 , H01L27/1025
摘要： An improved semiconductor integrated circuit device having an array of integrated injection logic memory cells arranged in matrix form, with word and bit lines connected to the memory cells arranged in lines. The second word line is formed by a semiconductor bulk, and dummy cells each comprising a shunt circuit for shunting the write current of the memory cells and a hold circuit for supplying a hold current to the memory cells are arranged in each line of the memory array.
摘要翻译：一种改进的半导体集成电路器件，其具有以矩阵形式布置的集成注入逻辑存储器单元的阵列，其中字线和位线连接到排列成行的存储器单元。第二字线由半导体体形成，并且每个包括用于分流存储单元的写入电流的分流电路和用于向存储单元提供保持电流的保持电路的虚拟单元被布置在存储器阵列的每一行中。

10. 发明授权

US06826712B2 Memory device having redundant cells 失效
标题翻译：具有冗余单元的存储器件
公开(公告)号：US06826712B2
公开(公告)日：2004-11-30
申请号：US09783554
申请日：2001-02-15
申请人： Chikai Ono
发明人： Chikai Ono
IPC分类号： G06F1100
CPC分类号： G11C29/789 , G11C11/22
摘要： According to an aspect of the present invention, a redundant file memory for recording first replacement information having an address of a defective cell to be replaced with a redundant cell is configured by a memory cell having the same configuration as an ordinary memory cell, and when accessing the ordinary memory cell, the redundant file memory can be accessed at the same time. Furthermore, second replacement information indicating whether or not the ordinary cell in correspondence with the stored address is a defective one is recorded in the redundant file memory. When accessing the ordinary memory cell, the first and second replacement information recorded in the redundant file memory are read out at the same time, and the defective cell is replaced with the redundant cell according to the replacement information.
摘要翻译：根据本发明的一个方面，用于记录具有由冗余单元替代的缺陷单元的地址的第一替换信息的冗余文件存储器由具有与普通存储单元相同配置的存储单元配置，并且当访问普通存储单元，可以同时访问冗余文件存储器。此外，指示与存储的地址相对应的普通小区是否是有缺陷的第二替换信息被记录在冗余文件存储器中。当访问普通存储单元时，同时读出记录在冗余文件存储器中的第一和第二替换信息，并根据替换信息用冗余单元替换缺陷单元。

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