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1. 发明授权

US5989754A Photomask arrangement protecting reticle patterns from electrostatic discharge damage (ESD) 失效
标题翻译：保护掩模版图案免受静电放电损坏（ESD）的光掩模布置
公开(公告)号：US5989754A
公开(公告)日：1999-11-23
申请号：US923980
申请日：1997-09-05
申请人： Shih-Shiung Chen , Ming-Fa Chen , Ho-Ku Lan , Ying-Chen Chao
发明人： Shih-Shiung Chen , Ming-Fa Chen , Ho-Ku Lan , Ying-Chen Chao
IPC分类号： G03F1/00 , G03F1/40 , G03F9/00
CPC分类号： G03F1/40
摘要： A photomask arrangement is disclosed to prevent the reticle patterns of a photomask from peeling caused by electrostatic discharge damage. The photomask includes: a substrate; a plurality of metal shielding layers formed on the surface of the substrate to provide the reticle patterns, wherein each two of the metal shielding layers are spaced apart by a clear scribe line; and a plurality of metal lines formed on the clear scribe line to connect the adjacent metal shielding layers, thereby increasing the effective surface area of the reticle patterns.
摘要翻译：公开了一种光掩模布置，以防止光掩模的掩模版图案由静电放电损坏引起的剥离。光掩模包括：基底; 形成在所述基板表面上的多个金属屏蔽层，以提供所述标线图案，其中每个所述金属屏蔽层通过清晰的划线间隔开; 以及形成在清晰划线上的多条金属线，以连接相邻的金属屏蔽层，从而增加标线图案的有效表面积。

2. 发明授权

US5999397A Method for preventing electrostatic discharge damage to an insulating article 失效
标题翻译：防止静电放电损坏绝缘物品的方法
公开(公告)号：US5999397A
公开(公告)日：1999-12-07
申请号：US958531
申请日：1997-10-27
申请人： Ming-Fa Chen , Shih-Shiung Chen , Ying-Chen Chao
发明人： Ming-Fa Chen , Shih-Shiung Chen , Ying-Chen Chao
IPC分类号： G03F7/20 , H05F1/00
CPC分类号： G03F1/66 , G03F7/70741 , H05F1/00
摘要： The present invention discloses a method for preventing electrostatic discharge damages to an article that is made of an insulating material and stored in a container also made of an insulating material by maintaining a minimum safe distance between the article and the top lid of the container such that a saturation electric field cannot be reached at such safety distance and thus electrostatic discharge does not occur. The present invention novel method can be utilized in carrying any insulating articles but is particularly suitable for carrying a quartz reticle in a polycarbonate pod.
摘要翻译：本发明公开了一种防止对由绝缘材料制成的物品的静电放电损坏的方法，并且通过保持物品与容器顶盖之间的最小安全距离而将其储存在也由绝缘材料制成的容器中，使得在这样的安全距离处不能达到饱和电场，因此不会发生静电放电。本发明的新颖方法可用于承载任何绝缘制品，但特别适用于在聚碳酸酯荚中承载石英掩模版。

3. 发明授权

US5798192A Structure of a mask for use in a lithography process of a semiconductor fabrication 失效
标题翻译：用于半导体制造的光刻工艺中的掩模的结构
公开(公告)号：US5798192A
公开(公告)日：1998-08-25
申请号：US834330
申请日：1997-04-15
申请人： Ming-Chu King , Shih-Shiung Chen , Ying-Chen Chao
发明人： Ming-Chu King , Shih-Shiung Chen , Ying-Chen Chao
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F1/40 , G03F1/50
摘要： A structure of a mask for use in a lithography process in a semiconductor fabrication procedure is disclosed. The structure comprising: a mask base being made of transparent material; a plurality of patterns formed on said mask base, said patterns being used for generating an image on a wafer and being made of a conductive opaque material; and a conductive layer formed on said mask base and said plurality of patterns.
摘要翻译：公开了一种用于半导体制造过程中的光刻工艺中的掩模的结构。该结构包括：掩模基底，由透明材料制成; 形成在所述掩模基底上的多个图案，所述图案用于在晶片上产生图像并由导电不透明材料制成; 以及形成在所述掩模基底和所述多个图案上的导电层。

4. 发明授权

US5807787A Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation 失效
标题翻译：在聚酰亚胺钝化期间减少半导体集成电路上的表面泄漏电流的方法
公开(公告)号：US5807787A
公开(公告)日：1998-09-15
申请号：US755862
申请日：1996-12-02
申请人： Wen-Jui Fu , Ho-Ku Lan , Ying-Chen Chao
发明人： Wen-Jui Fu , Ho-Ku Lan , Ying-Chen Chao
IPC分类号： H01L21/311 , H01C21/4762
CPC分类号： H01L21/31138 , Y10S438/974
摘要： A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.
摘要翻译：在形成图案化的聚酰亚胺钝化层之后，实现了一种降低集成电路基板上的相邻焊盘之间的表面泄漏电流的方法。当将聚酰亚胺层图案化以在接合焊盘上打开接触区域时，使用氧气中的等离子体灰化来除去残留的聚酰亚胺，否则会导致高接触电阻和较差的芯片产量。该等离子体灰化还修改接合焊盘之间的绝缘层，导致焊盘之间的表面泄漏电流的不期望的增加。通过在等离子体灰化之后在氮气或空气环境中使用热处理步骤来基本上消除增加的表面泄漏电流并提高芯片产量来改善钝化过程。

5. 发明授权

US5757060A Contamination guard ring for semiconductor integrated circuit applications 失效
标题翻译：用于半导体集成电路应用的防污环
公开(公告)号：US5757060A
公开(公告)日：1998-05-26
申请号：US684072
申请日：1996-07-19
申请人： Jin-Yuan Lee , John Chih-Shih Wei , Ying-Chen Chao
发明人： Jin-Yuan Lee , John Chih-Shih Wei , Ying-Chen Chao
IPC分类号： H01L23/525 , H01L23/544 , H01L29/41
CPC分类号： H01L23/5258 , H01L23/5256 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： The guard ring is a barrier which prevents contaminates from diffusing through a window opening through insulating layers to adjacent semiconductor devices. The guard ring is formed surrounding a window in the insulation layers over a fuse link or an alignment mark. The guard ring is an annular metal ring that penetrates two or more insulating layers and contacts the substrate.
摘要翻译：防护环是防止污染物通过绝缘层通过窗口扩散到相邻半导体器件的屏障。保护环形成在保险丝层或对准标记之间的绝缘层中的窗口周围。保护环是穿过两个或更多个绝缘层并与衬底接触的环形金属环。

6. 发明授权

US5685947A Chemical-mechanical polishing with an embedded abrasive 失效
标题翻译：用嵌入式磨料进行化学机械抛光
公开(公告)号：US5685947A
公开(公告)日：1997-11-11
申请号：US510827
申请日：1995-08-03
申请人： Huan Chi Tseng , Ying-Chen Chao
发明人： Huan Chi Tseng , Ying-Chen Chao
IPC分类号： B24B37/04 , B24B57/02 , H01L21/3105 , H01L21/461
CPC分类号： B24B37/04 , B24B57/02 , H01L21/31053
摘要： A chemical-mechanical polishing process is described that provides high etch rates while at the same time minimizing the consumption of abrasives. This is achieved by embedding and dispersing the abrasive within the body of the material that is to be subjected to chemical-mechanical polishing.
摘要翻译：描述了提供高蚀刻速率同时使磨料的消耗最小化的化学机械抛光工艺。这是通过将磨料嵌入和分散在待进行化学机械抛光的材料的主体内来实现的。

7. 发明授权

US5674357A Semiconductor substrate cleaning process 失效
标题翻译：半导体衬底清洗工艺
公开(公告)号：US5674357A
公开(公告)日：1997-10-07
申请号：US521454
申请日：1995-08-30
申请人： Yi-Lin Sun , Ying-Chen Chao
发明人： Yi-Lin Sun , Ying-Chen Chao
IPC分类号： H01L21/02 , H01L21/306 , H01L21/3213 , H01L21/302
CPC分类号： H01L21/02054 , H01L21/02071
摘要： A method for removing particulate residues from semiconductor substrates. A semiconductor substrate is provided which has upon its surface a particulate residue. At minimum, either the semiconductor substrate or the particulate residue is susceptible to oxidation upon exposure to an oxygen containing plasma. The semiconductor substrate and the particulate residue are exposed to an oxygen plasma. The particulates are then rinsed from the surface of the semiconductor substrate with deionized water.
摘要翻译：一种从半导体衬底去除微粒残留物的方法。提供半导体衬底，其表面上具有颗粒残留物。至少，半导体衬底或颗粒残留物在暴露于含氧等离子体时易于氧化。将半导体衬底和颗粒残余物暴露于氧等离子体。然后用去离子水从颗粒表面漂洗微粒。

8. 发明授权

US5591673A Tungsten stud process for stacked via applications 失效
标题翻译：用于堆叠通孔应用的钨螺柱工艺
公开(公告)号：US5591673A
公开(公告)日：1997-01-07
申请号：US498356
申请日：1995-07-05
申请人： Ying-Chen Chao , Chih-Heng Shen , Yi-Dong Yan
发明人： Ying-Chen Chao , Chih-Heng Shen , Yi-Dong Yan
IPC分类号： H01L21/311 , H01L21/768 , H01L21/283 , H01L21/302
CPC分类号： H01L21/76877 , H01L21/31116
摘要： A tungsten stud, stacked via process, has been developed, featuring smooth planar topographies at all metal levels. The desirable topography is obtained by allowing the tungsten stud to reside at the same level, or slightly above the level, of the top surface of the via hole insulator. This is achieved via an insulator etch back procedure, performed after metal stud formation.
摘要翻译：已经开发了一种钨丝螺柱，堆叠过程，在所有金属水平上都具有平滑的平面形貌。通过使钨螺柱位于通孔绝缘体的顶表面的相同水平或略高于水平面的位置获得所需的形貌。这通过绝缘体回蚀程序实现，在金属螺柱形成之后进行。

9. 发明授权

US6024831A Method and apparatus for monitoring plasma chamber condition by observing plasma stability 失效
标题翻译：通过观察等离子体稳定性来监测等离子体室条件的方法和装置
公开(公告)号：US6024831A
公开(公告)日：2000-02-15
申请号：US915212
申请日：1997-08-20
申请人： Yuan-Ko Hwang , Ying-Chen Chao
发明人： Yuan-Ko Hwang , Ying-Chen Chao
IPC分类号： H01J37/32 , G06F15/18 , H01L21/00
CPC分类号： H01J37/32935 , H01J37/32972
摘要： A method and apparatus for monitoring condition of the plasma of a plasma process during processing is disclosed. A spectrum detector (12) detects the intensity of a predetermined wavelength of radiation produced by the plasma process. The output of the spectrum detector is sampled, filtered, and normalized. A parameter calculator (20) calculates a parameter such as velocity or acceleration of the intensity. The calculated parameter is compared to a predetermined threshold. If the parameter exceeds the predetermined threshold, an error condition is indicated.
摘要翻译：公开了一种在处理期间监测等离子体工艺的等离子体状态的方法和装置。光谱检测器（12）检测由等离子体处理产生的辐射的预定波长的强度。对频谱检测器的输出进行采样，滤波和归一化。参数计算器（20）计算强度的速度或加速度等参数。将计算的参数与预定阈值进行比较。如果参数超过预定阈值，则指示错误状态。

10. 发明授权

US5780315A Dry etch endpoint method 失效
标题翻译：干蚀刻终点法
公开(公告)号：US5780315A
公开(公告)日：1998-07-14
申请号：US816478
申请日：1997-03-13
申请人： Ying-Chen Chao , Ting-Hwang Lin
发明人： Ying-Chen Chao , Ting-Hwang Lin
IPC分类号： H01J37/32 , H01L21/3213 , H01L21/66 , H01L21/302
CPC分类号： B24B37/013 , H01J37/32935 , H01J37/32963 , H01L21/32135 , H01L22/26 , Y10S438/963
摘要： An improved method for selecting etch endpoint when dry etching conductive material layers for use in semiconductor device circuits has been created. The more precise endpoint selection procedure produces metallization patterns which are free from residues (resulting from under-etching) and free from sidewall attack and/or pattern degradation (resulting from over-etching). The method avoids costly and time consuming pre-sorting of substrates according to product pattern density.
摘要翻译：已经创建了用于在半导体器件电路中使用干蚀刻导电材料层时选择蚀刻端点的改进方法。更精确的端点选择过程产生不含残留物（由蚀刻下产生）并且没有侧壁侵蚀和/或图案退化（由过度蚀刻产生）的金属化图案。该方法根据产品图案密度避免了成本高且耗时的基片预分选。

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