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1. 发明授权

US5726497A Upward plug filled via hole device 失效
标题翻译：向上插塞填充通孔装置
公开(公告)号：US5726497A
公开(公告)日：1998-03-10
申请号：US627842
申请日：1996-04-03
申请人： Ying-Chen Chao , Ting-Hwang Lin , Jin-Yuan Lee
发明人： Ying-Chen Chao , Ting-Hwang Lin , Jin-Yuan Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/52 , B32B9/04 , B32B15/04 , H01L29/12
CPC分类号： H01L23/53223 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , Y10S257/915 , Y10T428/12736 , Y10T428/12806 , Y10T428/26
摘要： A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.
摘要翻译：一种在硅半导体衬底上制造半导体器件的方法包括在半导体衬底上形成第一应力层，在第一应力层上形成互连层，在互连层上形成第二应力层，形成在第二应力层上的金属间电介质（IMD）层，图案化和蚀刻通过金属间介电层的通孔开口和暴露金属互连层表面上的接触区域的第二应力层，足以将金属互连层挤压到通孔中的温度。

2. 发明授权

US5541131A Peeling free metal silicide films using ion implantation 失效
标题翻译：使用离子注入剥离游离金属硅化物膜
公开(公告)号：US5541131A
公开(公告)日：1996-07-30
申请号：US649549
申请日：1991-02-01
申请人： Chue-San Yoo , Ting-Hwang Lin
发明人： Chue-San Yoo , Ting-Hwang Lin
IPC分类号： H01L21/285 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28518 , Y10S148/147
摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the polycide peeling problems. A pattern of gate electrode structures is formed upon a semiconductor substrate which each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. This causes the formation of a thin layer of silicon dioxide upon the exposed silicon substrate, the exposed polysilicon layer and the exposed metal silicide layer. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces and spacer structures formed by anisotropic etching. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The silicon oxide layer on the top surface of the metal silicate layer was removed by etching. Silicon ions are now implanted into the metal silicide layer to supply an excess of silicon ions at the surface of the metal silicide layer. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover.
摘要翻译：描述了一种制造轻掺杂漏极MOSFET集成电路器件的方法，其克服了多晶硅剥离问题。栅电极结构的图案形成在半导体衬底上，每个半导体衬底包括栅极氧化物，多晶硅层和非晶难熔金属硅化物。此时可以在氧气中对所得结构进行退火，以将难熔金属硅化物从其沉积的非晶相变为其结晶相。这导致在暴露的硅衬底，暴露的多晶硅层和暴露的金属硅化物层上形成薄的二氧化硅层。通过使用多晶硅栅极结构作为掩模的离子注入形成衬底中的轻掺杂区域的图案。介电层被覆盖在各个表面上，并通过各向异性蚀刻形成间隔结构。通过使用具有间隔结构的聚硅氧烷结构作为掩模的离子注入形成衬底中的重掺杂区域的图案，以产生MOSFET器件的轻掺杂漏极/漏极结构。通过蚀刻去除金属硅酸盐层的顶表面上的氧化硅层。硅离子现在被注入到金属硅化物层中，以在金属硅化物层的表面处提供过量的硅离子。通过在所描述的结构上形成钝化层并在其上形成适当的电连接结构来完成集成电路器件。

3. 发明授权

US5385868A Upward plug process for metal via holes 失效
标题翻译：金属通孔向上插入工艺
公开(公告)号：US5385868A
公开(公告)日：1995-01-31
申请号：US270668
申请日：1994-07-05
申请人： Ying-Chen Chao , Ting-Hwang Lin , Jin-Yuan Lee
发明人： Ying-Chen Chao , Ting-Hwang Lin , Jin-Yuan Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/48
CPC分类号： H01L23/53223 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , Y10S257/915 , Y10T428/12736 , Y10T428/12806 , Y10T428/26
摘要： A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.
摘要翻译：一种在硅半导体衬底上制造半导体器件的方法包括在半导体衬底上形成第一应力层，在第一应力层上形成互连层，在互连层上形成第二应力层，形成在第二应力层上的金属间电介质（IMD）层，图案化和蚀刻通过金属间介电层的通孔开口和暴露金属互连层表面上的接触区域的第二应力层，足以将金属互连层挤压到通孔中的温度。

4. 发明授权

US5203957A Contact sidewall tapering with argon sputtering 失效
标题翻译：氩气溅射接触侧壁逐渐变细
公开(公告)号：US5203957A
公开(公告)日：1993-04-20
申请号：US713508
申请日：1991-06-12
申请人： Chue-San Yoo , Ting-Hwang Lin , Sui-Hei Kuo
发明人： Chue-San Yoo , Ting-Hwang Lin , Sui-Hei Kuo
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76826 , H01L21/31116 , H01L21/76804
摘要： The method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less is accomplished by first providing an integrated circuit structure having device elements within a semiconductor substate and multilayer insulating layers thereover. A resist masking layer is formed over the multilayer insulating layer having openings therein in the areas where the contact openings are desired. Isotropic etching is done through a desired thickness portion of multilayer insulating layer. Anisotropic etching is now done through the remaining thickness of multilayer insulating layer to the semiconductor substrate to form the desired contact opening. The resist layer is removed. The structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of multilayer layer and the point where the isotropic etching ended and the anisotropic etching began. It is preferred that soft reactive ion etching be done for a period of less than about 30 seconds after said Argon sputter etching to reduce the increased contact resistance caused by this Argon sputter etching.
摘要翻译：通过首先提供具有在半导体子状态内的器件元件和其上的多层绝缘层的集成电路结构，来实现具有约1微米或更小特征尺寸的集成电路的接触开口的方法。在需要接触开口的区域中，在其上具有开口的多层绝缘层上形成抗蚀剂掩模层。通过多层绝缘层的所需厚度部分进行各向同性蚀刻。现在通过多层绝缘层的剩余厚度到半导体衬底来形成各向异性蚀刻以形成所需的接触开口。去除抗蚀剂层。该结构经受氩溅射蚀刻环境以平滑多层层的上表面处的尖角以及各向同性蚀刻结束的点和各向异性蚀刻开始。优选的是，在所述氩溅射蚀刻之后，软反应离子蚀刻进行时间小于约30秒，以减少由该氩溅射蚀刻引起的增加的接触电阻。

5. 发明授权

US5780315A Dry etch endpoint method 失效
标题翻译：干蚀刻终点法
公开(公告)号：US5780315A
公开(公告)日：1998-07-14
申请号：US816478
申请日：1997-03-13
申请人： Ying-Chen Chao , Ting-Hwang Lin
发明人： Ying-Chen Chao , Ting-Hwang Lin
IPC分类号： H01J37/32 , H01L21/3213 , H01L21/66 , H01L21/302
CPC分类号： B24B37/013 , H01J37/32935 , H01J37/32963 , H01L21/32135 , H01L22/26 , Y10S438/963
摘要： An improved method for selecting etch endpoint when dry etching conductive material layers for use in semiconductor device circuits has been created. The more precise endpoint selection procedure produces metallization patterns which are free from residues (resulting from under-etching) and free from sidewall attack and/or pattern degradation (resulting from over-etching). The method avoids costly and time consuming pre-sorting of substrates according to product pattern density.
摘要翻译：已经创建了用于在半导体器件电路中使用干蚀刻导电材料层时选择蚀刻端点的改进方法。更精确的端点选择过程产生不含残留物（由蚀刻下产生）并且没有侧壁侵蚀和/或图案退化（由过度蚀刻产生）的金属化图案。该方法根据产品图案密度避免了成本高且耗时的基片预分选。

6. 发明授权

US5646071A Equipment and method for applying a liquid layer 失效
标题翻译：用于涂敷液体层的设备和方法
公开(公告)号：US5646071A
公开(公告)日：1997-07-08
申请号：US374856
申请日：1995-01-19
申请人： Ting-Hwang Lin , Shih-Ming Wang , Li-Chum Chen
发明人： Ting-Hwang Lin , Shih-Ming Wang , Li-Chum Chen
IPC分类号： B05D1/00 , H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/465 , B05D3/12
CPC分类号： B05D1/005 , H01L21/31051 , H01L21/316
摘要： A method and apparatus for applying a liquid to the surface of semiconductor wafer are described. The wafer is rotated about an axis; perpendicular to its main surface. Liquid is dispensed onto the surface of the spinning wafer from at least two dispensing bottles. One of the dispensing bottles is positioned above the center of rotation while the others are located between it and the wafer's edge. The rate at which liquid emerges from each of the dispensing bottles is independently controlled for each bottle.
摘要翻译：描述了一种将液体施加到半导体晶片的表面的方法和装置。晶片围绕轴旋转; 垂直于其主表面。液体从至少两个分配瓶分配到旋转晶片的表面上。其中一个分配瓶定位在旋转中心之上，而另一个位于其与晶片的边缘之间。从每个分配瓶中排出液体的速率对于每个瓶独立地被控制。

7. 发明授权

US5413940A Process of treating SOG layer using end-point detector for outgassing 失效
标题翻译：使用终点检测器对SOG层进行脱气处理
公开(公告)号：US5413940A
公开(公告)日：1995-05-09
申请号：US320895
申请日：1994-10-11
申请人： Chung-An Lin , Ting-Hwang Lin , Ying-Chen Chao
发明人： Chung-An Lin , Ting-Hwang Lin , Ying-Chen Chao
IPC分类号： H01L21/312 , H01L21/316 , H01L21/3213
CPC分类号： H01L21/316 , H01L21/3121
摘要： Disclosed is a method of integrated circuit manufacture involving a method for optimizing the time needed to outgas a layer of spin-on-glass. A layer of spin-on-glass that was previously covered over may be exposed again as a result of subsequent processing. It is necessary to subject such a layer to an outgassing treatment by heating it in vacuum prior to the deposition of a metal film which could react with any ougassed material that was not already removed. To avoid having to heat the integrated circuit for any longer than is absolutely necessary during outgassing, the partial pressure of the outgassed material is monitored by means of a residual gas analyzer whose output is used to control the outgassing process.
摘要翻译：公开了一种集成电路制造方法，其涉及一种优化蒸发旋涂玻璃层所需时间的方法。先前被覆盖的一层旋涂玻璃可能由于后续处理而再次曝光。在沉积可能与任何未被去除的任何被淹没的材料发生反应的金属膜沉积之前，必须通过在真空中对其进行加热来进行除气处理。为了避免在除气过程中绝热需要加热集成电路，通过残留气体分析仪来监测脱气材料的分压，其输出用于控制除气过程。

8. 发明授权

US5393685A Peeling free metal silicide films using rapid thermal anneal 失效
标题翻译：使用快速热退火剥离游离金属硅化物膜
公开(公告)号：US5393685A
公开(公告)日：1995-02-28
申请号：US926299
申请日：1992-08-10
申请人： Chue-San Yoo , Ting-Hwang Lin
发明人： Chue-San Yoo , Ting-Hwang Lin
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28518
摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which provides a peeling-free metal silicide gate electrode devices. The process uses annealing of the gate oxide, the polysilicon layer and the metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000.degree. C. and for a time of between about 30 to 60 seconds. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Driving in the pattern of lightly doped regions is accomplished by rapid thermal annealing at a temperature of more than about 1000.degree. C. and for a time of between about 30 to 60 seconds with the metal silicide layer having no covering thereover. Heavily doped regions are now formed in the substrate to produce the lightly doped drain under the spacer structure of an MOS FET device. A passivation layer is formed over the structures and electrical connecting structures thereover.
摘要翻译：描述了一种制造提供无剥离金属硅化物栅电极器件的轻掺杂漏极MOSFET集成电路器件的方法。该方法使用快速热退火工艺在大于约1000℃的温度和大约30至60秒的时间内对栅极氧化物，多晶硅层和金属硅化物层进行退火。通过使用该结构作为掩模的离子注入在衬底中形成轻掺杂区域的图案。低温二氧化硅层被覆盖在该结构的表面上。蚀刻覆盖层以在每个栅电极结构的侧壁上和衬底的相邻部分之上形成介电间隔物结构，并从金属硅化物层的顶表面去除氧化硅层。通过在大于约1000℃的温度下快速热退火并且在其间没有覆盖的金属硅化物层的时间为约30至60秒之间来实现轻掺杂区域的驱动。现在在衬底中形成重掺杂区域，以在MOS FET器件的间隔结构之下产生轻掺杂漏极。在其上的结构和电连接结构上形成钝化层。

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