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1. 发明申请

US20100207191A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20100207191A1
公开(公告)日：2010-08-19
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

2. 发明授权

US08637918B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08637918B2
公开(公告)日：2014-01-28
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

3. 发明授权

US08076199B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08076199B2
公开(公告)日：2011-12-13
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

4. 发明申请

US20120056260A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20120056260A1
公开(公告)日：2012-03-08
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

5. 发明授权

US08487373B2 SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same 有权
标题翻译：具有不均匀隧道氧化物的SONOS存储单元及其制造方法
公开(公告)号：US08487373B2
公开(公告)日：2013-07-16
申请号：US12432441
申请日：2009-04-29
申请人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
发明人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
IPC分类号： H01L21/331
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/42352
摘要： Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
摘要翻译：公开了形成存储单元的方法。一种方法包括在半导体衬底中形成源极 - 漏极结构，其中源极 - 漏极结构包括圆顶顶表面和侧壁表面。在源极 - 漏极结构的顶壁和侧壁表面上形成氧化物层。形成在源极 - 漏极结构的顶表面上的氧化物层的部分的厚度大于在源极 - 漏极结构的侧壁表面上形成的氧化物层的部分的厚度。

6. 发明授权

US08987092B2 Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges 有权
标题翻译：用于制造具有半圆形顶表面和圆角顶角和边缘的鳍结构的存储单元的方法
公开(公告)号：US08987092B2
公开(公告)日：2015-03-24
申请号：US12110974
申请日：2008-04-28
申请人： Inkuk Kang , Gang Xue , Shenqing Fang , Rinji Sugino , Yi Ma
发明人： Inkuk Kang , Gang Xue , Shenqing Fang , Rinji Sugino , Yi Ma
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L29/78
CPC分类号： H01L27/11568 , H01L29/66795 , H01L29/7854
摘要： Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.
摘要翻译：公开了制造具有半圆顶表面和圆顶顶表面拐角和边缘的FIN结构的方法。作为所公开的方法的一部分，在半导体衬底中形成FIN结构。 FIN结构包括具有拐角和边缘的顶表面。 FIN结构退火，其中退火导致顶表面具有半圆形形状，并且顶表面拐角和边缘被倒圆。

7. 发明授权

US08551858B2 Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory 有权
标题翻译：自对准SI丰富的氮化物电荷陷阱层隔离电荷陷阱闪存
公开(公告)号：US08551858B2
公开(公告)日：2013-10-08
申请号：US12699635
申请日：2010-02-03
申请人： Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
发明人： Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
IPC分类号： H01L21/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/76224 , H01L27/11568
摘要： A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.
摘要翻译：公开了一种在圆形有源区域角上制造具有U形陷阱层的存储器件的方法。在本发明中，在形成电荷俘获层之前进行STI工艺。在STI处理之后，活动区域的尖角暴露，使其可用于四舍五入。四舍五入改善了存储设备的性能特征。在舍入处理之后，形成底部氧化物层，氮化物层和牺牲顶部氧化物层。施加到电荷捕获层的有机底部抗反射涂层被平坦化。现在蚀刻有机底部抗反射涂层，牺牲顶部氧化物层和氮化物层，而不在有源区域上蚀刻牺牲顶部氧化物层和氮化物层。在蚀刻之后，电荷捕获层具有横截面的U形外观。 U形陷阱层边缘允许增加堆积密度和集成度，同时保持捕集层之间的隔离。

8. 发明授权

US07122465B1 Method for achieving increased control over interconnect line thickness across a wafer and between wafers 有权
标题翻译：用于实现跨晶片和晶片之间的互连线厚度的增加的控制的方法
公开(公告)号：US07122465B1
公开(公告)日：2006-10-17
申请号：US11003208
申请日：2004-12-02
申请人： Boon-Yong Ang , Cinti Xiaohua Chen , Simon S. Chan , Inkuk Kang
发明人： Boon-Yong Ang , Cinti Xiaohua Chen , Simon S. Chan , Inkuk Kang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/3212 , H01L21/7684
摘要： According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.
摘要翻译：根据一个示例性实施例，一种方法包括蚀刻ILD层中的沟槽的步骤，所述沟槽具有侧壁和底表面。该方法还包括确定沟槽的侧壁的高度。该方法还包括用互连金属填充沟槽，使得互连金属在沟槽之上延伸。根据该示例性实施例，该方法还包括执行CMP处理以去除互连金属的一部分。在本发明中，利用沟槽侧壁的高度来控制在CMP工艺中执行的抛光量。沟槽中的互连金属的剩余部分形成互连线，其中通过利用沟槽的侧壁的高度来控制互连线的厚度以控制CMP工艺中的抛光量。

9. 发明授权

US06963108B1 Recessed channel 有权
标题翻译：嵌入渠道
公开(公告)号：US06963108B1
公开(公告)日：2005-11-08
申请号：US10683631
申请日：2003-10-10
申请人： Inkuk Kang , Hiroyuki Kinoshita , Jeff P. Erhardt , Emmanuil H. Lingunis
发明人： Inkuk Kang , Hiroyuki Kinoshita , Jeff P. Erhardt , Emmanuil H. Lingunis
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/04 , H01L29/78 , H01L29/792
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/045 , H01L29/66621 , H01L29/66833 , H01L29/7835 , H01L29/792
摘要： A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench region. A gate dielectric layer is formed in the trench region of the semiconductor substrate between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A control gate is formed on the semiconductor substrate above the recessed channel region, wherein the control gate is separated from the recessed channel region by the gate dielectric layer.
摘要翻译：描述了具有减小的短通道效应的存储单元。在半导体衬底中形成沟槽区。源极区域和漏极区域形成在沟槽区域的相对侧上，其中源极区域的底部和漏极区域的底部在沟槽区域的地板的上方。在源极区域和漏极区域之间的半导体衬底的沟槽区域中形成栅极电介质层。在沟槽区域，源极区域和漏极区域之下形成凹陷沟道区域。控制栅极形成在凹陷沟道区域上方的半导体衬底上，其中控制栅极通过栅极介电层与凹陷沟道区分离。

10. 发明授权

US06803275B1 ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices 有权
标题翻译： ONO制造工艺，用于降低闪存器件底部氧化层中的氧空位
公开(公告)号：US06803275B1
公开(公告)日：2004-10-12
申请号：US10308518
申请日：2002-12-03
申请人： Jaeyong Park , Hidehiko Shiraiwa , Arvind Halliyal , Jean Y. Yang , Inkuk Kang , Tazrien Kamal , Amir H. Jafarpour
发明人： Jaeyong Park , Hidehiko Shiraiwa , Arvind Halliyal , Jean Y. Yang , Inkuk Kang , Tazrien Kamal , Amir H. Jafarpour
IPC分类号： H01L21336
CPC分类号： H01L29/66833 , H01L21/28282 , H01L21/3144
摘要： Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer. In another embodiment, a process for fabricating a SONOS flash memory device includes forming a bottom oxide layer of an ONO structure on the semiconductor substrate under strongly oxidizing conditions, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.
摘要翻译：在一个实施例中，包括在半导体衬底上形成ONO结构的底部氧化物层的SONOS闪速存储器件的制造方法，其中底部氧化物层具有第一氧空位含量; 处理底部氧化物层以将第一氧空位含量降低至第二氧空位含量; 以及在底部氧化物层上沉积介电电荷存储层。在另一个实施例中，制造SONOS闪速存储器件的工艺包括在强氧化条件下在半导体衬底上形成ONO结构的底部氧化物层，其中底部氧化物层具有超化学计量的氧含量和氧空位含量降低相对于通过常规方法形成的底部氧化物层; 以及在底部氧化物层上沉积介电电荷存储层。

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