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1. 发明申请

US20120056260A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20120056260A1
公开(公告)日：2012-03-08
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

2. 发明申请

US20100207191A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20100207191A1
公开(公告)日：2010-08-19
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

3. 发明授权

US08637918B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08637918B2
公开(公告)日：2014-01-28
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

4. 发明授权

US08076199B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08076199B2
公开(公告)日：2011-12-13
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

5. 发明申请

US20090104745A1 INTEGRATION METHOD FOR DUAL DOPED POLYSILICON GATE PROFILE AND CD CONTROL 审中-公开
标题翻译：双重多晶硅门型材和CD控制的集成方法
公开(公告)号：US20090104745A1
公开(公告)日：2009-04-23
申请号：US11877124
申请日：2007-10-23
申请人： Hyesook Hong , Luigi Colombo , Jinhan Choi
发明人： Hyesook Hong , Luigi Colombo , Jinhan Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/823842
摘要： In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of polysilicon gates having a first critical dimension disposed over a dielectric layer and planarizing the plurality of polysilicon gates with a spin-on material to form a plurality of planarized polysilicon gates. The method can further include doping an exposed first region with p-type dopants to form a plurality of p-doped planarized polysilicon gates and doping an exposed second region with n-type dopants to form a plurality of n-doped planarized polysilicon gates. The method can also include removing the spin-on material to form a plurality of p-doped polysilicon gates and a plurality of n-doped polysilicon gates, wherein critical dimension of each of the plurality of n-doped polysilicon gates and the plurality of p-doped polysilicon gates are substantially similar to the first critical dimension.
摘要翻译：根据本教导，提供制造双掺杂多晶硅栅极的方法。该方法可以包括提供包括多个多晶硅栅极的半导体结构，该多晶硅栅极具有设置在电介质层上的第一临界尺寸，并且用旋涂材料平坦化多个多晶硅栅极以形成多个平坦化的多晶硅栅极。该方法还可以包括用p型掺杂剂掺杂暴露的第一区域以形成多个p掺杂的平坦化多晶硅栅极，并用n型掺杂剂掺杂暴露的第二区域以形成多个n掺杂的平坦化多晶硅栅极。该方法还可以包括去除旋涂材料以形成多个p掺杂多晶硅栅极和多个n掺杂多晶硅栅极，其中多个n掺杂多晶硅栅极和多个p掺杂多晶硅栅极中的每一个的临界尺寸掺杂的多晶硅栅极基本上类似于第一临界尺寸。

6. 发明授权

US07244642B2 Method to obtain fully silicided gate electrodes 有权
公开(公告)号：US07244642B2
公开(公告)日：2007-07-17
申请号：US11228902
申请日：2005-09-16
申请人： Steven A. Vitale , Hyesook Hong , Freidoon Mehrad
发明人： Steven A. Vitale , Hyesook Hong , Freidoon Mehrad
IPC分类号： H01L21/337 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/469 , H01L21/31
CPC分类号： H01L21/823425 , H01L21/823443 , H01L21/823835
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255). Source/drains are formed adjacent the gate electrodes 250 and through the remnant of the spacer material (415), and a metal is incorporated into the gate electrodes (250).

7. 发明申请

US20050164096A1 Monitor for variation of critical dimensions (CDs) of reticles 有权
标题翻译：监测光栅的关键尺寸（CD）的变化
公开(公告)号：US20050164096A1
公开(公告)日：2005-07-28
申请号：US10630332
申请日：2003-07-30
申请人： Hyesook Hong , Zhiliu Ma , John Wright
发明人： Hyesook Hong , Zhiliu Ma , John Wright
IPC分类号： G03F1/14 , G03F7/20 , G03F9/00 , G03F1/00
CPC分类号： G03F1/78 , G03F1/44 , G03F1/68
摘要： The present invention provides a reticle 100 for use in a lithographic process. The reticle, in one embodiment, includes a patterned layer 110 located over a reticle substrate. The reticle 100 may further include a test pattern 130 located over the reticle substrate, wherein a portion of the test pattern 130 is within a step-distance of a portion of the patterned layer. In this embodiment, a variance in the test pattern is indicative of a variance in the patterned layer.
摘要翻译：本发明提供一种用于光刻工艺的掩模版100。在一个实施例中，掩模版包括位于掩模版基板上方的图案层110。掩模版100还可以包括位于掩模版基板上方的测试图案130，其中测试图案130的一部分在图案层的一部分的步距内。在该实施例中，测试图案中的方差表示图案层中的变化。

8. 发明授权

US08198105B2 Monitor for variation of critical dimensions (CDs) of reticles 有权
标题翻译：监测光栅的关键尺寸（CD）的变化
公开(公告)号：US08198105B2
公开(公告)日：2012-06-12
申请号：US10630332
申请日：2003-07-30
申请人： Hyesook Hong , Zhiliu Ma , John K. Wright
发明人： Hyesook Hong , Zhiliu Ma , John K. Wright
IPC分类号： H01L21/66 , G01N21/00 , G03F1/00 , G21K5/10
CPC分类号： G03F1/78 , G03F1/44 , G03F1/68
摘要： The present invention provides a reticle 100 for use in a lithographic process. The reticle, in one embodiment, includes a patterned layer 110 located over a reticle substrate. The reticle 100 may further include a test pattern 130 located over the reticle substrate, wherein a portion of the test pattern 130 is within a step-distance of a portion of the patterned layer. In this embodiment, a variance in the test pattern is indicative of a variance in the patterned layer.
摘要翻译：本发明提供一种用于光刻工艺的掩模版100。在一个实施例中，掩模版包括位于掩模版基板上方的图案层110。掩模版100还可以包括位于掩模版基板上方的测试图案130，其中测试图案130的一部分在图案层的一部分的步距内。在该实施例中，测试图案中的方差表示图案层中的变化。

9. 发明申请

US20050255687A1 Plasma treatment for silicon-based dielectrics 有权
标题翻译：硅基电介质的等离子体处理
公开(公告)号：US20050255687A1
公开(公告)日：2005-11-17
申请号：US10843957
申请日：2004-05-11
申请人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
发明人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02123 , H01L21/0234 , H01L21/3105 , H01L21/316 , H01L21/76807 , H01L21/76808
摘要： An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).
摘要翻译：本发明的一个实施例是制造半导体晶片的方法。该方法包括在半导体晶片上沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤210），施加蒸发（步骤212），在旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214），然后蚀刻半导体晶片（步骤216）。本发明的另一实施例是在半导体晶片上制造双镶嵌后端层的方法。该方法包括在电介质层上和通孔内沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤（步骤212），在所述旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214）和蚀刻沟槽空间（步骤216）。

10. 发明授权

US06605536B2 Treatment of low-k dielectric films to enable patterning of deep submicron features 有权
公开(公告)号：US06605536B2
公开(公告)日：2003-08-12
申请号：US10143314
申请日：2002-05-10
申请人： Mona Eissa , Guoqiang Xing , Kenneth D. Brennan , Hyesook Hong
发明人： Mona Eissa , Guoqiang Xing , Kenneth D. Brennan , Hyesook Hong
IPC分类号： H01L2144
CPC分类号： H01L21/76826 , H01L21/31058 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/76808 , H01L21/76835
摘要： Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H2SO4) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130,132). The wet treatment is performed to either pre-treat a low-k dielectric (104) before forming the pattern (130,132) or during a rework of the pattern (130,132) to reduce resist poisoning.

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