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1. 发明授权

US08987092B2 Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges 有权
标题翻译：用于制造具有半圆形顶表面和圆角顶角和边缘的鳍结构的存储单元的方法
公开(公告)号：US08987092B2
公开(公告)日：2015-03-24
申请号：US12110974
申请日：2008-04-28
申请人： Inkuk Kang , Gang Xue , Shenqing Fang , Rinji Sugino , Yi Ma
发明人： Inkuk Kang , Gang Xue , Shenqing Fang , Rinji Sugino , Yi Ma
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L29/78
CPC分类号： H01L27/11568 , H01L29/66795 , H01L29/7854
摘要： Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.
摘要翻译：公开了制造具有半圆顶表面和圆顶顶表面拐角和边缘的FIN结构的方法。作为所公开的方法的一部分，在半导体衬底中形成FIN结构。 FIN结构包括具有拐角和边缘的顶表面。 FIN结构退火，其中退火导致顶表面具有半圆形形状，并且顶表面拐角和边缘被倒圆。

2. 发明申请

US20100207191A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20100207191A1
公开(公告)日：2010-08-19
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

3. 发明授权

US08637918B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08637918B2
公开(公告)日：2014-01-28
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

4. 发明授权

US08487373B2 SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same 有权
标题翻译：具有不均匀隧道氧化物的SONOS存储单元及其制造方法
公开(公告)号：US08487373B2
公开(公告)日：2013-07-16
申请号：US12432441
申请日：2009-04-29
申请人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
发明人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
IPC分类号： H01L21/331
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/42352
摘要： Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
摘要翻译：公开了形成存储单元的方法。一种方法包括在半导体衬底中形成源极 - 漏极结构，其中源极 - 漏极结构包括圆顶顶表面和侧壁表面。在源极 - 漏极结构的顶壁和侧壁表面上形成氧化物层。形成在源极 - 漏极结构的顶表面上的氧化物层的部分的厚度大于在源极 - 漏极结构的侧壁表面上形成的氧化物层的部分的厚度。

5. 发明授权

US08076199B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08076199B2
公开(公告)日：2011-12-13
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

6. 发明授权

US08551858B2 Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory 有权
标题翻译：自对准SI丰富的氮化物电荷陷阱层隔离电荷陷阱闪存
公开(公告)号：US08551858B2
公开(公告)日：2013-10-08
申请号：US12699635
申请日：2010-02-03
申请人： Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
发明人： Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
IPC分类号： H01L21/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/76224 , H01L27/11568
摘要： A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.
摘要翻译：公开了一种在圆形有源区域角上制造具有U形陷阱层的存储器件的方法。在本发明中，在形成电荷俘获层之前进行STI工艺。在STI处理之后，活动区域的尖角暴露，使其可用于四舍五入。四舍五入改善了存储设备的性能特征。在舍入处理之后，形成底部氧化物层，氮化物层和牺牲顶部氧化物层。施加到电荷捕获层的有机底部抗反射涂层被平坦化。现在蚀刻有机底部抗反射涂层，牺牲顶部氧化物层和氮化物层，而不在有源区域上蚀刻牺牲顶部氧化物层和氮化物层。在蚀刻之后，电荷捕获层具有横截面的U形外观。 U形陷阱层边缘允许增加堆积密度和集成度，同时保持捕集层之间的隔离。

7. 发明申请

US20120056260A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20120056260A1
公开(公告)日：2012-03-08
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

8. 发明授权

US08202779B2 Methods for forming a memory cell having a top oxide spacer 有权
标题翻译：形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US08202779B2
公开(公告)日：2012-06-19
申请号：US12891310
申请日：2010-09-27
申请人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
发明人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

9. 发明授权

US08384146B2 Methods for forming a memory cell having a top oxide spacer 有权
标题翻译：形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US08384146B2
公开(公告)日：2013-02-26
申请号：US13428848
申请日：2012-03-23
申请人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
发明人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

10. 发明授权

US09128780B2 Validating license servers in virtualized environments 有权
标题翻译：验证虚拟化环境中的许可证服务器
公开(公告)号：US09128780B2
公开(公告)日：2015-09-08
申请号：US13402121
申请日：2012-02-22
申请人： Gang Xue , Qiufang Shi
发明人： Gang Xue , Qiufang Shi
IPC分类号： G06F15/16 , G06F9/00 , G06F17/00 , G06F7/04 , G06F12/00 , G06F12/14 , G06F13/00 , G06F17/30 , G11C7/00 , H04L29/06 , G06F9/52 , H04L29/08 , G06F3/06 , H04W4/00 , G06F21/10 , G06F21/73
CPC分类号： G06F9/526 , G06F3/067 , G06F17/30197 , G06F17/302 , G06F21/10 , G06F21/73 , G06F2221/0704 , H04L29/08549 , H04L63/08 , H04L63/10 , H04W4/60
摘要： The present invention extends to methods, systems, and computer program products for validating license servers in virtualized environments. Embodiments of the invention leverage a set of features acquired or built in cloud computing environments to facilitate a software based solution providing uniqueness and immutability of a license server hosted in the cloud. Avoiding features of the underlying hardware systems results a much more flexible and reliable platform for hosting license servers. Features of a cloud storage service can be used to create a unique ID for a license server. Security and reliability of license servers hosted in a pubic cloud environment is also improved.
摘要翻译：本发明扩展到用于在虚拟化环境中验证许可证服务器的方法，系统和计算机程序产品。本发明的实施例利用在云计算环境中获取或构建的一组特征来促进基于软件的解决方案，从而提供托管在云中的许可证服务器的唯一性和不可变性。避免底层硬件系统的功能为托管许可证服务器带来了更加灵活和可靠的平台。可以使用云存储服务的功能为许可证服务器创建唯一的ID。托管在公共云环境中的许可证服务器的安全性和可靠性也得到提高。

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