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1. 发明授权

US06934789B2 Interface, structure and method for transmitting data of PCI bus which uses bus request signal for judging whether a device supporting dual transmission mode 有权
标题翻译：用于发送PCI总线数据的接口，结构和方法，该总线使用总线请求信号来判断是否支持双传输模式的设备
公开(公告)号：US06934789B2
公开(公告)日：2005-08-23
申请号：US09894684
申请日：2001-06-27
申请人： Sheng-Chang Peng , Chau-Chad Tsai , Hsuan-Yi Wang , Chi-Che Tsai
发明人： Sheng-Chang Peng , Chau-Chad Tsai , Hsuan-Yi Wang , Chi-Che Tsai
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/423
摘要： A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.
摘要翻译：公开了一种用于发送PCI总线的数据的总线数据接口，结构和方法。总线数据接口包括高位发送缓冲器，低位发送缓冲器，复用器，选通发生器和数据分配器。选通发生器利用总线请求信号和总线许可信号来响应于PCI时钟发送数据选通信号。根据数据选通信号的上升沿和下降沿，数据分配器根据数据选通信号检索数据。此外，本发明与原始PCI总线兼容，并允许PCI总线以双速传输数据。

2. 发明授权

US06925517B2 Bus for supporting plural signal line configurations and switch method thereof 有权
标题翻译：用于支持多信号线配置的总线及其切换方法
公开(公告)号：US06925517B2
公开(公告)日：2005-08-02
申请号：US10249361
申请日：2003-04-03
申请人： Sheng-Chang Peng , Chau-Chad Tsai , Chih-kuo Kao , Chi-Che Tsai
发明人： Sheng-Chang Peng , Chau-Chad Tsai , Chih-kuo Kao , Chi-Che Tsai
IPC分类号： H04L5/16 , G06F13/14 , G06F13/40
CPC分类号： H04L5/16
摘要： A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.
摘要翻译：用于支持多个信号线配置的总线及其切换方法，用于在控制芯片之间的总线中操作以保持其操作灵活性。当控制芯片之间的数据传输负载适用于双向传输时，选择双向传输的信号线配置。当双向传输方向频繁切换时，选择其他信号线配置。也就是说，总线信号线分为两部分，每个部分负责每个单向的数据传输，以避免影响传输性能的转向周期。

3. 发明授权

US06721833B2 Arbitration of control chipsets in bus transaction 有权
标题翻译：总线交易中控制芯片组的仲裁
公开(公告)号：US06721833B2
公开(公告)日：2004-04-13
申请号：US09735412
申请日：2000-12-12
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
IPC分类号： G06F1336
CPC分类号： G06F13/36
摘要： A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.
摘要翻译：一种控制芯片组内的总线仲裁方法，控制芯片组还包括第一控制芯片和第二控制芯片，数据通过总线在第一和第二控制芯片之间传输，总线包括双向总线第一控制芯片通常控制使用总线的权限，但第二个控制芯片具有使用总线的优先级。伴随总线规格无等待周期，仲裁权限使用总线可以快速，毫无错误地完成。因此，不需要GNT信号线，仲裁时间缩短。

4. 发明授权

US06684284B1 Control chipset, and data transaction method and signal transmission devices therefor 有权
标题翻译：控制芯片组，数据交易方法及信号传输装置
公开(公告)号：US06684284B1
公开(公告)日：2004-01-27
申请号：US09718811
申请日：2000-11-22
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
IPC分类号： G06F944
CPC分类号： G06F13/4027
摘要： A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the status of the buffers within another control chips. When a control chip asserts a command, the corresponding data must be ready in advance. Therefore, the signal line for providing the waiting status, data transaction cycle and stop/retry protocol can be omitted. Accordingly, commands or data can be continuously transmitted without waiting, stop or retry, the performance is improved.
摘要翻译：控制芯片之间的数据交易方法。控制芯片组的控制芯片的数据缓冲器具有固定的尺寸和数量。此外，读/写确认命令根据读/写命令依次被断言，通过该命令，控制芯片可以检测另一个控制芯片内的缓冲器的状态。当控制芯片发出命令时，相应的数据必须提前准备就绪。因此，可以省略用于提供等待状态，数据事务周期和停止/重试协议的信号线。因此，可以连续发送命令或数据，而无需等待，停止或重试，提高性能。

5. 发明授权

US06678771B1 Method of adjusting an access sequencing scheme for a number of PCI- compliant units coupled to a PCI bus system 有权
标题翻译：调整与PCI总线系统耦合的多个PCI兼容单元的接入排序方案的方法
公开(公告)号：US06678771B1
公开(公告)日：2004-01-13
申请号：US09687225
申请日：2000-10-13
申请人： Chau-Chad Tsai , Wen-Hao Chuang , Chi-Che Tsai
发明人： Chau-Chad Tsai , Wen-Hao Chuang , Chi-Che Tsai
IPC分类号： G06F100
CPC分类号： G06F13/423
摘要： A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units are associated respectively with a set of request signals that allow these PCI-compliant units to request the use of the PCI bus system for data transfer. The access sequencing scheme includes a first-layer access sequence loop and a second-layer access sequence loop, with the first-layer access sequence loop having a higher priority over the second-layer access sequence loop The request signals are assigned to either the first-layer access sequence loop or the second-layer access sequence loop in a predetermined manner. The user can change the assignment of a certian request signal from one loop to the other through PC's BIOS (Basic Input/Output System), so as to allow the associated PCI-compliant unit to have a higher priority level to the use of the PCI bus system.
摘要翻译：一种用于调整与计算机系统上的PCI总线系统耦合的多个PCI（外围组件互连）兼容单元的接入排序方案的方法。这些PCI兼容单元分别与一组请求信号相关联，这些请求信号允许这些PCI兼容单元请求使用PCI总线系统进行数据传输。接入排序方案包括第一层接入序列循环和第二层接入序列循环，其中第一层接入序列循环具有比第二层接入序列循环更高的优先权。请求信号被分配给第一层层次访问序列循环或第二层访问序列循环。用户可以通过PC的BIOS（基本输入/输出系统）通过PC的BIOS（基本输入/输出系统）将一个循环的一个循环的分配更改为另一个循环，从而允许相关的PCI兼容单元对PCI的使用具有更高的优先级总线系统。

6. 发明授权

US08060676B2 Method of hot switching data transfer rate on bus 有权
标题翻译：总线上热切换数据传输速率的方法
公开(公告)号：US08060676B2
公开(公告)日：2011-11-15
申请号：US11433195
申请日：2006-05-11
申请人： Chau-Chad Tsai , Chi-Che Tsai , Chih-kuo Kao
发明人： Chau-Chad Tsai , Chi-Che Tsai , Chih-kuo Kao
IPC分类号： G06F13/42 , G06F5/06 , G06F13/36
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.
摘要翻译：本发明提供了一种在总线上热切换数据传输速率的方法，以热切换控制芯片之间的总线的数据传输速率，而无需复位。当控制芯片之间的总线需要大量的数据传输时，总线被热切换到更高的数据传输速率，以满足数据传输的要求。相反，当控制芯片之间的总线需要更少的数据传输量时，总线被热切换到较低的数据传输速率以节省功耗。

7. 发明授权

US07051148B2 Data transmission sequencing method associated with briding device and application system 有权
公开(公告)号：US07051148B2
公开(公告)日：2006-05-23
申请号：US10055558
申请日：2002-01-22
申请人： Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai , Wen-Hao Chuang , Chun-Yuan Su
发明人： Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai , Wen-Hao Chuang , Chun-Yuan Su
IPC分类号： G06F13/36 , G06F13/42
CPC分类号： G06F13/4059
摘要： A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

8. 发明授权

US06622213B2 Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions 有权
标题翻译：用于使用第一和第二高速缓存数据区将存储器单元与外围设备连接的双向缓存系统和方法
公开(公告)号：US06622213B2
公开(公告)日：2003-09-16
申请号：US09881861
申请日：2001-06-15
申请人： Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
发明人： Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
IPC分类号： G06F1300
CPC分类号： G06F12/0846
摘要： A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit. The cache system has a two-way first-in first-out buffer region and a two-way cache controller. The two-way first-in first-out buffer region further has a first cache data region and a second cache data region. The first cache data region and the second cache data region are capable of holding a batch of first cache data and a batch of second cache data. The two-way cache controller receives a read request from the peripheral device. According to the read request, the requested data and data that ensues or comes after the requested data are retained by the two-way first-in first-out buffer (FIFO) region. If the peripheral device continues to request more data by maintaining a FRAME signal line in an enabled state, the first cache data region and the second cache data region are alternately used to read in subsequent data. A check may be made to see if requested data stored inside the two-way cache buffer region is coherent or consistent with data stored inside the memory unit.
摘要翻译：一种用于与外围设备进行接口的双向缓存系统和一种操作双向高速缓存系统以在外围设备和存储器单元之间进行数据传输的方法。缓存系统具有双向先进先出缓冲区和双向缓存控制器。双向先入先出缓冲区还具有第一缓存数据区和第二缓存数据区。第一高速缓存数据区域和第二高速缓存数据区域能够保存一批第一高速缓存数据和一批第二高速缓存数据。双向缓存控制器从外围设备接收读请求。根据该读取请求，所请求的数据和所请求数据之后的数据由双向先入先出缓冲器（FIFO）区域保留。如果外围设备通过将FRAME信号线保持在使能状态继续请求更多的数据，则第一高速缓存数据区域和第二高速缓存数据区域被交替地用于在随后的数据中读取。可以进行检查以查看存储在双向高速缓存缓冲区内的请求数据是否与存储在存储器单元内的数据相一致或一致。

9. 发明授权

US07136955B2 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US07136955B2
公开(公告)日：2006-11-14
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/00 , G06F13/20 , G06F13/36
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

10. 发明授权

US07107373B2 Method of hot switching data transfer rate on bus 有权
公开(公告)号：US07107373B2
公开(公告)日：2006-09-12
申请号：US10065524
申请日：2002-10-25
申请人： Chau-Chad Tsai , Chi-Che Tsai , Chih-Kuo Kao
发明人： Chau-Chad Tsai , Chi-Che Tsai , Chih-Kuo Kao
IPC分类号： G06F13/42 , G06F5/06
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

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