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1. 发明授权

US06721833B2 Arbitration of control chipsets in bus transaction 有权
标题翻译：总线交易中控制芯片组的仲裁
公开(公告)号：US06721833B2
公开(公告)日：2004-04-13
申请号：US09735412
申请日：2000-12-12
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
IPC分类号： G06F1336
CPC分类号： G06F13/36
摘要： A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.
摘要翻译：一种控制芯片组内的总线仲裁方法，控制芯片组还包括第一控制芯片和第二控制芯片，数据通过总线在第一和第二控制芯片之间传输，总线包括双向总线第一控制芯片通常控制使用总线的权限，但第二个控制芯片具有使用总线的优先级。伴随总线规格无等待周期，仲裁权限使用总线可以快速，毫无错误地完成。因此，不需要GNT信号线，仲裁时间缩短。

2. 发明授权

US06684284B1 Control chipset, and data transaction method and signal transmission devices therefor 有权
标题翻译：控制芯片组，数据交易方法及信号传输装置
公开(公告)号：US06684284B1
公开(公告)日：2004-01-27
申请号：US09718811
申请日：2000-11-22
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
IPC分类号： G06F944
CPC分类号： G06F13/4027
摘要： A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the status of the buffers within another control chips. When a control chip asserts a command, the corresponding data must be ready in advance. Therefore, the signal line for providing the waiting status, data transaction cycle and stop/retry protocol can be omitted. Accordingly, commands or data can be continuously transmitted without waiting, stop or retry, the performance is improved.
摘要翻译：控制芯片之间的数据交易方法。控制芯片组的控制芯片的数据缓冲器具有固定的尺寸和数量。此外，读/写确认命令根据读/写命令依次被断言，通过该命令，控制芯片可以检测另一个控制芯片内的缓冲器的状态。当控制芯片发出命令时，相应的数据必须提前准备就绪。因此，可以省略用于提供等待状态，数据事务周期和停止/重试协议的信号线。因此，可以连续发送命令或数据，而无需等待，停止或重试，提高性能。

3. 发明授权

US07136955B2 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US07136955B2
公开(公告)日：2006-11-14
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/00 , G06F13/20 , G06F13/36
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

4. 发明申请

US20050097254A1 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US20050097254A1
公开(公告)日：2005-05-05
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/36 , G06F13/38
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块

5. 发明授权

US06546448B1 Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master 有权
标题翻译：用于通过多功能主机中的多个功能来仲裁对PCI总线的访问的方法和装置
公开(公告)号：US06546448B1
公开(公告)日：2003-04-08
申请号：US09440764
申请日：1999-11-16
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
IPC分类号： G06F1314
CPC分类号： G06F13/362
摘要： Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.
摘要翻译：用于通过多功能主机中的多个功能来仲裁对pci总线的访问的方法和装置。在多功能主机的多个功能之间执行仲裁方法。仲裁器包括旋转查询调度程序（RIS）和启发式查询启动器（HII）。 RIS从功能电路接收本地查询信号并存储。根据本地查询信号，生成总线查询信号并将其发送到HII，并发送到PCI总线以请求使用PCI总线。如果PCI总线响应延迟事务终止，则HII可以将总线查询信号重复发送到PCI总线，直到PCI总线授予使用PCI总线的权限。然后，HII通知RIS，该RIS将功能电路通过PCI总线传输数据。

6. 发明授权

US07051148B2 Data transmission sequencing method associated with briding device and application system 有权
公开(公告)号：US07051148B2
公开(公告)日：2006-05-23
申请号：US10055558
申请日：2002-01-22
申请人： Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai , Wen-Hao Chuang , Chun-Yuan Su
发明人： Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai , Wen-Hao Chuang , Chun-Yuan Su
IPC分类号： G06F13/36 , G06F13/42
CPC分类号： G06F13/4059
摘要： A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

7. 发明授权

US06694400B1 PCI system controller capable of delayed transaction 有权
标题翻译： PCI系统控制器能够延迟交易
公开(公告)号：US06694400B1
公开(公告)日：2004-02-17
申请号：US09451121
申请日：1999-11-30
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
IPC分类号： G06F1338
CPC分类号： G06F13/4217
摘要： A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with respect to the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator, indicating that the request has been accepted. When the requested data is ready in the responder, the responder will forward the defer identifier again. The initiator picks up the defer identifier and prepares according to the buffer identifier in it. Then, data transmission between the initiator and the responder begins.
摘要翻译：在PCI系统及其相关设备上进行延迟数据交易的方法。延迟数据事务使用PCI系统在启动器和应答器之间传输数据。启动器和应答器都与PCI总线相连。 PCI系统中的延迟事务包括多个步骤。首先，启动器将发出使用PCI总线的请求，以便可以对响应者进行数据传输。如果响应者接受请求但不能足够快地保护所请求的数据，则响应者将生成对应于请求的发起者的延迟标识符。接下来，由响应者生成的停止信号和延迟标识符将被返回给启动器，指示该请求已被接受。当请求的数据在响应者中准备就绪时，响应者将再次转发延迟标识符。发起人拿起延迟标识符，并根据缓冲区标识符进行准备。然后，启动器和应答器之间的数据传输开始。

8. 发明授权

US06549964B1 Delayed transaction method and device used in a PCI system 有权
公开(公告)号：US06549964B1
公开(公告)日：2003-04-15
申请号：US09451820
申请日：1999-11-30
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
IPC分类号： G06F1300
CPC分类号： G06F13/4226
摘要： A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

9. 发明授权

US06941398B2 Processing method, chip set and controller for supporting message signaled interrupt 有权
标题翻译：处理方法，芯片组和控制器支持消息信号中断
公开(公告)号：US06941398B2
公开(公告)日：2005-09-06
申请号：US09826784
申请日：2001-04-04
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Min-Hung Chen , Meng-Cheng Ku , Huei-Li Chou
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Min-Hung Chen , Meng-Cheng Ku , Huei-Li Chou
IPC分类号： G06F13/24 , G06F13/14
CPC分类号： G06F13/24 , G06F2213/2418
摘要： A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.
摘要翻译：一种处理方法，芯片组和用于支持消息信号中断的控制器。监视PCI总线上的存储器写事务。当在写事务的中断消息中指定的系统存储器的地址位于保留的中断地址的范围时，执行中断服务序列。保留的中断地址位于系统存储器的地址中。因此，要处理的数据和系统指定的消息被写入缓冲器中并且按顺序排列。解决了“写缓冲区延迟”的问题，与PCI总线的级别无关。许多系统指定的消息可以存储在系统存储器中，从而可以在相同的中断服务程序中处理来自不同外设组件的多个系统消息信号中断。

10. 发明授权

US07805567B2 Chipset and northbridge with raid access 有权
标题翻译：芯片组和北桥与突袭访问
公开(公告)号：US07805567B2
公开(公告)日：2010-09-28
申请号：US11854576
申请日：2007-09-13
申请人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
发明人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
IPC分类号： G06F12/00
CPC分类号： G06F13/4027 , G06F11/1076 , G06F2211/1054
摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.
摘要翻译：在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。此外，北桥通过南桥进一步融合到RAID。北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

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