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1. 发明授权

US06713831B1 Borderless contact architecture 有权
标题翻译：无边界联络体系
公开(公告)号：US06713831B1
公开(公告)日：2004-03-30
申请号：US10010837
申请日：2001-12-04
申请人： Sharmin Sadoughi , Mira Ben-Tzur , Michal E. Fastow , Saurabh Dutta Chowdhury
发明人： Sharmin Sadoughi , Mira Ben-Tzur , Michal E. Fastow , Saurabh Dutta Chowdhury
IPC分类号： H01L310232
CPC分类号： H01L21/76829 , H01L21/0276 , H01L21/31144 , H01L21/3212 , H01L21/76897 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.
摘要翻译：提供了一种用于形成无边界接触结构的方法和系统。特别地，提供了一种方法，其包括使用无机抗反射涂层作为蚀刻停止物以形成无边界接触结构。在一些实施例中，该方法可以包括以具有抗反射特性的方式对无机层上方的互连线进行图案化，并且在互连线上方沉积上部层间电介质层。然后可以在上层间介质层内蚀刻沟槽，使得可以形成与所述互连线接触的无边界接触结构。因此，在这样的实施例中，提供半导体形貌，其包括布置在互连线下方的无机抗反射涂层和布置在互连线上的接触结构。在一些实施例中，接触结构的宽度可以大于互连线的宽度。

2. 发明授权

US06841878B1 Integrated circuit with improved RC delay 有权
标题翻译：具有改善RC延迟的集成电路
公开(公告)号：US06841878B1
公开(公告)日：2005-01-11
申请号：US10672895
申请日：2003-09-26
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Alain Blosse , Fuad Badrieh
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Alain Blosse , Fuad Badrieh
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/48
CPC分类号： H01L21/32051 , H01L21/76829 , H01L21/76837 , H01L21/76838
摘要： In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.
摘要翻译：在一个实施例中，钝化层包括低k电介质。低k电介质有助于降低金属线在最后一个金属电平的电容，这可能刚好低于钝化水平。在另一个实施例中，金属线相对较厚。这有助于降低金属线的电阻并导致RC延迟。

3. 发明授权

US06939792B1 Low-k dielectric layer with overlying adhesion layer 有权
标题翻译：具有上覆粘合层的低k电介质层
公开(公告)号：US06939792B1
公开(公告)日：2005-09-06
申请号：US10402865
申请日：2003-03-28
申请人： Maryam Jahangiri , Mira Ben-Tzur
发明人： Maryam Jahangiri , Mira Ben-Tzur
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/318 , H01L21/469 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76837 , H01L21/31058 , H01L21/31608 , H01L21/3185 , H01L21/76829 , Y10S438/958
摘要： In one embodiment, a method of fabricating an integrated circuit includes forming a low-k dielectric layer over metal lines, forming an adhesion layer over the low-k dielectric layer, and forming a capping layer over the adhesion layer. The low-k dielectric may comprise SiLK™ dielectric material, while the capping layer may comprise TEOS. The resulting stack of dielectric materials may be employed in a passivation level to protect the metal lines. For example, a topside layer may be formed over the capping layer.
摘要翻译：在一个实施例中，制造集成电路的方法包括在金属线上形成低k电介质层，在低k电介质层上形成粘合层，并在粘合层上形成覆盖层。低k电介质可以包括SiLK TM介电材料，而封盖层可以包括TEOS。所得到的电介质材料叠层可用于钝化层以保护金属线。例如，可以在覆盖层上形成顶层。

4. 发明授权

US07227212B1 Method of forming a floating metal structure in an integrated circuit 有权
标题翻译：在集成电路中形成浮动金属结构的方法
公开(公告)号：US07227212B1
公开(公告)日：2007-06-05
申请号：US11021220
申请日：2004-12-23
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Ikeuchi
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Ikeuchi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76885 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L28/87 , H01L2924/0002 , Y10S257/924 , H01L2924/00
摘要： In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.
摘要翻译：在一个实施例中，牺牲层沉积在基底层上。牺牲层用于限定随后形成的浮动金属结构。浮动金属结构可以锚定到基层中。一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。

5. 发明授权

US07192867B1 Protection of low-k dielectric in a passivation level 有权
标题翻译：保护低k电介质在钝化水平
公开(公告)号：US07192867B1
公开(公告)日：2007-03-20
申请号：US10184336
申请日：2002-06-26
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Seurabh Dutta Chowdhury , Michal Efrati Fastow
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Seurabh Dutta Chowdhury , Michal Efrati Fastow
IPC分类号： H01L21/302
CPC分类号： H01L21/76831 , H01L21/76814
摘要： In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.
摘要翻译：在一个实施例中，钝化层包括低k电介质。为了防止低k电介质暴露于空气时吸收水分，低k电介质的暴露部分被间隔物覆盖。可以理解，这有助于低k电介质在钝化层中的集成。钝化层中的低k电介质有助于降低金属线路上的电容，从而减少RC延迟并增加信号传播速度。

6. 发明授权

US06835616B1 Method of forming a floating metal structure in an integrated circuit 有权
标题翻译：在集成电路中形成浮动金属结构的方法
公开(公告)号：US06835616B1
公开(公告)日：2004-12-28
申请号：US10059823
申请日：2002-01-29
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Keuchi
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Keuchi
IPC分类号： H01L218242
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76885 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L28/87 , H01L2924/0002 , Y10S257/924 , H01L2924/00
摘要： In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.
摘要翻译：在一个实施例中，牺牲层沉积在基底层上。牺牲层用于限定随后形成的浮动金属结构。浮动金属结构可以锚定到基层中。一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。

7. 发明授权

US07018942B1 Integrated circuit with improved RC delay 有权
公开(公告)号：US07018942B1
公开(公告)日：2006-03-28
申请号：US10988813
申请日：2004-11-15
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Alain Blosse , Fuad Badrieh
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Alain Blosse , Fuad Badrieh
IPC分类号： H01L21/469
CPC分类号： H01L23/5222 , H01L21/76837 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

8. 发明授权

US06903002B1 Low-k dielectric layer with air gaps 有权
标题翻译：具有气隙的低k电介质层
公开(公告)号：US06903002B1
公开(公告)日：2005-06-07
申请号：US10241236
申请日：2002-09-11
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Christopher A. Seams , Thurman J. Rodgers
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Christopher A. Seams , Thurman J. Rodgers
IPC分类号： H01L21/302 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/7682
摘要： In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.
摘要翻译：在一个实施例中，金属层包括多条金属线。低k电介质沉积在金属层上，使得气隙至少形成在两条金属线之间。低k介质的相对较低的介电常数降低金属线上的电容，而不管是否形成气隙。低k电介质中的气隙进一步降低了金属线路上的电容。减小的电容转换为较低的RC延迟和更快的信号传播速度。

9. 发明授权

US06844235B1 Reticle repeater monitor wafer and method for verifying reticles 有权
标题翻译：掩模版中继器监视器晶圆及验证标线的方法
公开(公告)号：US06844235B1
公开(公告)日：2005-01-18
申请号：US09920374
申请日：2001-07-31
申请人： Christopher M. Jones , Mira Ben-Tzur , Allen Fung
发明人： Christopher M. Jones , Mira Ben-Tzur , Allen Fung
IPC分类号： G01N21/956 , G03F1/00 , H01L21/301 , H01L21/44 , H01L21/461 , H01L21/76
CPC分类号： G03F1/84 , G01N21/95607 , Y10S438/945
摘要： According to one embodiment, verifying a reticle may include patterning an inspected layer (102-2) according to a reticle pattern, depositing a contrast enhancing layer (104-0) on a patterned layer (102-2), and inspecting a reticle patterned formed in the inspected layer (102-2).
摘要翻译：根据一个实施例，验证掩模版可以包括根据掩模版图案图案化被检查层（102-2），在图案化层（102-2）上沉积对比度增强层（104-0），以及检查图案化的掩模版形成在检查层（102-2）中。

10. 发明授权

US06774033B1 Metal stack for local interconnect layer 有权
标题翻译：用于本地互连层的金属堆叠
公开(公告)号：US06774033B1
公开(公告)日：2004-08-10
申请号：US10287258
申请日：2002-11-04
申请人： Mira Ben-Tzur , Dafna Beery , Gorley L. Lau , Krishnaswamy Ramkumar
发明人： Mira Ben-Tzur , Dafna Beery , Gorley L. Lau , Krishnaswamy Ramkumar
IPC分类号： H01L214763
CPC分类号： H01L21/32051 , H01L21/76895
摘要： In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.
摘要翻译：在一个实施例中，通过在氧化物层上沉积第一膜并在第一膜上沉积第二膜来形成集成电路中的局部互连层。第一膜可以包括氮化钛，而第二膜可以包括例如钨。第一膜和第二膜可以通过溅射原位沉积。可以使用第一膜作为蚀刻停止来蚀刻第二膜，并且可以使用氧化物层作为蚀刻停止来蚀刻第一膜。

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