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    • 2. 发明授权
    • High temperature electrical connector
    • 高温电连接器
    • US06736668B1
    • 2004-05-18
    • US09663864
    • 2000-09-15
    • Arnold V. KholodenkoSenh ThachWing L. ChengAlvin LauDennis S. Grimard
    • Arnold V. KholodenkoSenh ThachWing L. ChengAlvin LauDennis S. Grimard
    • H01R1300
    • H01R13/533H01R2201/24
    • An electrical coupler comprises an inner connector having upper and lower ends, an insulative outer connector element circumscribing the inner connector, and a thermally conductive flange disposed over the upper end of the inner connector and the outer connector for conducting heat from the electrical conductor. The electrical conductor may be utilized in a substrate support for semiconductor wafer processing. The substrate support comprises a chuck body having an electrode embedded therein, and an upper male connector coupled to the electrode and protruding from said chuck body. A cooling plate having the electrical coupler is positioned proximate to the chuck body. The upper male connector is inserted in the electrical coupler, and a power source coupled to the lower portion of the electrical coupler chucks and biases a wafer to an upper surface of said chuck. The thermally conductive flange conducts and transfers heat generated from the upper male connector and electrical coupler to the cooling plate.
    • 电耦合器包括具有上端和下端的内连接器,限定内连接器的绝缘外连接器元件和设置在内连接器的上端上的导热凸缘和用于传导来自电导体的热的外连接器。 电导体可以用于半导体晶片处理的衬底支撑件中。 衬底支撑件包括具有嵌入其中的电极的卡盘体,以及耦合到电极并从所述卡盘体突出的上部阳连接器。 具有电耦合器的冷却板位于卡盘主体附近。 上部阳连接器插入电耦合器中,并且耦合到电耦合器的下部的电源卡住并将晶片偏置到所述卡盘的上表面。 导热凸缘传导和传递从上阳连接器和电耦合器产生的热量到冷却板。
    • 3. 发明授权
    • Apparatus for regulating temperature of a process kit in a semiconductor wafer-processing chamber
    • 用于调节半导体晶片处理室中的处理套件的温度的装置
    • US06795292B2
    • 2004-09-21
    • US09861984
    • 2001-05-15
    • Dennis GrimardArnold KholodenkoAlex VeytserSenh ThachWing Cheng
    • Dennis GrimardArnold KholodenkoAlex VeytserSenh ThachWing Cheng
    • H01G2300
    • H01L21/67109H01L21/67103
    • An apparatus for reducing by-product formation in a semiconductor wafer-processing chamber. In a first embodiment, the apparatus comprises a chuck having a chucking electrode and a radially extending peripheral flange. A collar is disposed over the peripheral flange defining a first gap therebetween, and circumscribes the chuck. A heater element is embedded within the collar and adapted for connection to a power source. In a second embodiment, the apparatus comprises a chuck having a chucking electrode and a radially extending peripheral flange, and a collar having a heater element embedded therein. The collar is disposed over the peripheral flange to define a gap therebetween, and circumscribes the chuck. Moreover, a pedestal having a gas delivery system therein is disposed below the chuck and collar. In a third embodiment, the apparatus comprises a chuck having a chucking electrode and a radially extending peripheral flange, a collar, and a waste ring having a heater element embedded therein. The waste ring is disposed over the peripheral flange defining a gap therebetween, and circumscribes the chuck. The collar is chucked to the waste ring, and the waste ring is chucked to a pedestal support. Moreover, the waste ring and pedestal each have a gas delivery system therein for regulating the temperature of the collar.
    • 一种用于减少半导体晶片处理室中副产物形成的装置。 在第一实施例中,该装置包括具有夹紧电极和径向延伸的周边凸缘的卡盘。 套环设置在周边凸缘之上,限定了它们之间的第一间隙,并限制卡盘。 加热器元件嵌入在轴环内并且适于连接到电源。 在第二实施例中,该装置包括具有夹紧电极和径向延伸的周边凸缘的卡盘以及嵌入其中的加热器元件的套环。 套环设置在周边凸缘上方以在其间形成间隙并限制卡盘。 此外,其中具有气体输送系统的基座设置在卡盘和轴环的下方。 在第三实施例中,该装置包括具有夹紧电极和径向延伸的周边凸缘,套环和具有嵌入其中的加热器元件的废料环的卡盘。 废环设置在周边凸缘之上,限定了它们之间的间隙,并且围绕卡盘。 将衣领卡在废物环上,将废物环卡在基座支架上。 此外,废环和底座各自具有用于调节套环温度的气体输送系统。
    • 5. 发明申请
    • Process kit for erosion resistance enhancement
    • 防腐蚀加工工艺套件
    • US20050016684A1
    • 2005-01-27
    • US10627213
    • 2003-07-25
    • Jennifer SunAnanda KumarSenh Thach
    • Jennifer SunAnanda KumarSenh Thach
    • H01L21/3065H01J37/32C23F1/00
    • H01J37/32477H01J37/32642
    • A process kit is described that resists plasma erosion, preserves the spatial uniformity of plasma properties, reduces particle generation in the chamber, and significantly enhances the lifetime of the process kit. A layer of polymer material covers the top surface of the process kit. The polymer material is fluorocarbon-based and not reactive with the species in the plasma. The polymer material not only protects the process kit from progressive erosion, but also prevents the generation of particles in the chamber. The polymer material has similar permittivity to that of the process kit and therefore maintains the spatial uniformity of plasma properties, e.g., etch rate, near the wafer perimeter. The thickness of the layer is controlled between 0.5 and 1.5 mm such that the difference between its coefficient of thermal expansion and that of the process kit will not cause the layer to peel off the process kit's top surface.
    • 描述了一种防止等离子体侵蚀的过程套件,保持了等离子体性质的空间均匀性,减少了腔室中的颗粒产生,并显着提高了工艺套件的使用寿命。 一层聚合物材料覆盖了工艺套件的顶面。 聚合物材料是基于碳氟化合物的,并且不与等离子体中的物质反应。 聚合物材料不仅可保护工艺套件免受逐渐侵蚀,还可防止腔室中产生颗粒。 聚合物材料具有与处理试剂盒相似的介电常数,因此在晶片周边附近保持等离子体特性(例如蚀刻速率)的空间均匀性。 将该层的厚度控制在0.5至1.5mm之间,使得其热膨胀系数与处理套件的热导率差不会导致该层从工艺套件的顶部表面剥离。
    • 10. 发明授权
    • System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
    • 系统级原位集成电介质蚀刻工艺特别适用于铜双镶嵌
    • US06949203B2
    • 2005-09-27
    • US10379439
    • 2003-03-03
    • Chang-Lin HsiehDiana Xiaobing MaBrian Sy Yuan ShiehGerald Zheyao YinJennifer SunSenh ThachLee LuoClaes H. Bjorkman
    • Chang-Lin HsiehDiana Xiaobing MaBrian Sy Yuan ShiehGerald Zheyao YinJennifer SunSenh ThachLee LuoClaes H. Bjorkman
    • H01L21/00H01L21/311H01L21/768
    • H01L21/76832H01J37/32458H01L21/31116H01L21/31138H01L21/67184H01L21/67207H01L21/67219H01L21/6723H01L21/76802H01L21/76804H01L21/76807
    • An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the barrier layer is etched through to the feature to be contacted in the second chamber of the multichamber substrate processing system using a process that discourages polymer formation over the relatively smooth interior surface of the second chamber. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps. In some embodiments the interior surface of the first chamber has a roughness between 100 and 200 Ra and in other embodiments the roughness of the first chamber's interior surface is between 110 and 160 Ra.
    • 在具有第一和第二蚀刻室的多室衬底处理系统中执行的集成原位蚀刻工艺。 在一个实施例中,第一室包括已经被粗糙化至少100个的内表面,而第二室包括具有小于约32μm的粗糙度的内表面, / SUB>。 该方法包括在向下的方向上转移其上形成有图案的光致抗蚀剂掩模,电介质层,阻挡层和衬底中的特征的衬底,以接触第一室,其中介电层被刻蚀在鼓励聚合物的过程中 在室的粗糙内表面上形成。 然后在真空条件下将衬底从第一室转移到第二室,并且在第二室中暴露于诸如氧的反应性等离子体以剥离沉积在衬底上的光致抗蚀剂掩模。 在光致抗蚀剂掩模被剥离之后,通过阻止在第二室的相对光滑的内表面上聚合物形成的工艺,阻挡层被蚀刻到多室基板处理系统的第二室中以接触的特征。 所有三个蚀刻步骤都是在系统级原位工艺中进行的,因此基板不会在台阶之间暴露于环境中。 在一些实施例中,第一室的内表面具有在100和200之间的粗糙度,而在其它实施例中,第一室的内表面的粗糙度在110和160之间, SUB>。