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1. 发明申请

US20070063763A1 Source transistor configurations and control methods 失效
标题翻译：源晶体管配置和控制方法
公开(公告)号：US20070063763A1
公开(公告)日：2007-03-22
申请号：US11483263
申请日：2006-07-06
申请人： Seung-Moon Yoo , Jae Yoo , Jeongduk Sohn , Sung Son , Myung Choi , Young Kim , Oh Yoon , Sang-Kyun Han
发明人： Seung-Moon Yoo , Jae Yoo , Jeongduk Sohn , Sung Son , Myung Choi , Young Kim , Oh Yoon , Sang-Kyun Han
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , G11C7/1045 , G11C11/4074 , G11C11/4076 , G11C2207/2227
摘要： Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.
摘要翻译：源晶体管配置被描述为减少集成电路内的泄漏和延迟。使用堆叠晶体管配置（例如在第一虚拟电源连接和VSS之间的两个晶体管堆叠）和第二虚拟电源连接和VDD之间来支持虚拟电源和接地节点。这些堆叠晶体管的栅极驱动器响应于电路的工作功率模式，例如主动模式，主动待机模式和深度掉电模式，以不同的电压电平进行调制。描述了用于驱动这些源堆栈的装置。在一个实施例中，单独的虚拟节点适用于不同类型的电路，例如缓冲器，行地址选通和列地址选通。还描述了诸如晶体管的定向放置的其它技术。

2. 发明授权

US07705625B2 Source transistor configurations and control methods 失效
标题翻译：源晶体管配置和控制方法
公开(公告)号：US07705625B2
公开(公告)日：2010-04-27
申请号：US11483263
申请日：2006-07-06
申请人： Seung-Moon Yoo , Jae Hoon Yoo , Jeongduk Sohn , Sung Ju Son , Myung Chan Choi , Young Tae Kim , Oh Sang Yoon , Sang-Kyun Han
发明人： Seung-Moon Yoo , Jae Hoon Yoo , Jeongduk Sohn , Sung Ju Son , Myung Chan Choi , Young Tae Kim , Oh Sang Yoon , Sang-Kyun Han
IPC分类号： H03K19/094
CPC分类号： H03K19/0016 , G11C7/1045 , G11C11/4074 , G11C11/4076 , G11C2207/2227
摘要： Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.
摘要翻译：源晶体管配置被描述为减少集成电路内的泄漏和延迟。使用堆叠晶体管配置（例如在第一虚拟电源连接和VSS之间的两个晶体管堆叠）和第二虚拟电源连接和VDD之间来支持虚拟电源和接地节点。这些堆叠晶体管的栅极驱动器响应于电路的工作功率模式，例如主动模式，主动待机模式和深度掉电模式，以不同的电压电平进行调制。描述了用于驱动这些源堆栈的装置。在一个实施例中，单独的虚拟节点适用于不同类型的电路，例如缓冲器，行地址选通和列地址选通。还描述了诸如晶体管的定向放置的其它技术。

3. 发明申请

US20080031068A1 DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS 失效
标题翻译：动态记忆刷新配置和泄漏控制方法
公开(公告)号：US20080031068A1
公开(公告)日：2008-02-07
申请号：US11779716
申请日：2007-07-18
申请人： Seung-Moon Yoo , Myung Choi , Sangho Shin , Sang-Kyun Han
发明人： Seung-Moon Yoo , Myung Choi , Sangho Shin , Sang-Kyun Han
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/4094 , G11C29/783 , G11C29/83 , G11C29/832 , G11C2211/4061 , G11C2211/4065 , G11C2211/4067 , G11C2211/4068
摘要： Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.
摘要翻译：描述了用于减少泄漏和提高修复产量的动态随机存取存储器（DRAM）电路和方法。根据本发明，通过在功率控制的单个激活中分组刷新周期，使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗，调制位线在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期，以及它们的组合。在一个方面，字线保险丝将使用模式指示为：未使用，替换，附加刷新以及附加刷新的替换。刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合，用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。

4. 发明授权

US07522464B2 Dynamic memory refresh configurations and leakage control methods 失效
标题翻译：动态内存刷新配置和泄漏控制方法
公开(公告)号：US07522464B2
公开(公告)日：2009-04-21
申请号：US11779716
申请日：2007-07-18
申请人： Seung-Moon Yoo , Myung Chan Choi , Sangho Shin , Sang-Kyun Han
发明人： Seung-Moon Yoo , Myung Chan Choi , Sangho Shin , Sang-Kyun Han
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/4094 , G11C29/783 , G11C29/83 , G11C29/832 , G11C2211/4061 , G11C2211/4065 , G11C2211/4067 , G11C2211/4068
摘要： Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.
摘要翻译：描述了用于减少泄漏和提高修复产量的动态随机存取存储器（DRAM）电路和方法。根据本发明，通过在功率控制的单个激活中分组刷新周期，使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗，调制位线在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期，以及它们的组合。在一个方面，字线保险丝将使用模式指示为：未使用，替换，附加刷新以及附加刷新的替换。刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合，用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。

5. 发明申请

US20070081405A1 LOW POWER MEMORY CONTROL CIRCUITS AND METHODS 失效
标题翻译：低功率存储器控制电路和方法
公开(公告)号：US20070081405A1
公开(公告)日：2007-04-12
申请号：US11534609
申请日：2006-09-22
申请人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
发明人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/20 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C2207/065 , G11C2207/2227 , G11C2211/4068 , H01L27/0207 , H01L27/10897
摘要： Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.
摘要翻译：描述用于抑制集成电路漏电流的电路和方法。这些电路和方法中的许多特别适用于动态存储器电路。示例描述了用于产生虚拟电压的电源，接地或两者以及电源和接地源晶体管的使用。本发明的一个方面描述降低刷新电流。一方面描述了减少待机电流。本发明的一个方面描述了降低由诸如行解码器和字线驱动器的复制电路产生的泄漏。一方面描述了执行源晶体管的早期唤醒的方法。教授了许多源晶体管控制机制。教导了使用源极晶体管优化集成电路布局的电路布局方法。

6. 发明申请

US20120201085A1 LOW POWER MEMORY CONTROL CIRCUITS AND METHODS 审中-公开
标题翻译：低功率存储器控制电路和方法
公开(公告)号：US20120201085A1
公开(公告)日：2012-08-09
申请号：US13089486
申请日：2011-04-19
申请人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Jung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
发明人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Jung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/20 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C2207/065 , G11C2207/2227 , G11C2211/4068 , H01L27/0207 , H01L27/10897
摘要： Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.
摘要翻译：描述用于抑制集成电路漏电流的电路和方法。这些电路和方法中的许多特别适用于动态存储器电路。示例描述了用于产生虚拟电压的电源，接地或两者以及电源和接地源晶体管的使用。本发明的一个方面描述降低刷新电流。一方面描述了减少待机电流。本发明的一个方面描述了降低由诸如行解码器和字线驱动器的复制电路产生的泄漏。一方面描述了执行源晶体管的早期唤醒的方法。教授了许多源晶体管控制机制。教导了使用源极晶体管优化集成电路布局的电路布局方法。

7. 发明授权

US07929367B2 Low power memory control circuits and methods 失效
标题翻译：低功耗存储器控制电路及方法
公开(公告)号：US07929367B2
公开(公告)日：2011-04-19
申请号：US11534609
申请日：2006-09-22
申请人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
发明人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/20 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C2207/065 , G11C2207/2227 , G11C2211/4068 , H01L27/0207 , H01L27/10897
摘要： Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.
摘要翻译：描述用于抑制集成电路漏电流的电路和方法。这些电路和方法中的许多特别适用于动态存储器电路。示例描述了用于产生虚拟电压的电源，接地或两者以及电源和接地源晶体管的使用。本发明的一个方面描述降低刷新电流。一方面描述了减少待机电流。本发明的一个方面描述了降低由诸如行解码器和字线驱动器的复制电路产生的泄漏。一方面描述了执行源晶体管的早期唤醒的方法。教授了许多源晶体管控制机制。教导了使用源极晶体管优化集成电路布局的电路布局方法。

8. 发明授权

US07190209B2 Low-power high-performance integrated circuit and related methods 有权
标题翻译：低功耗高性能集成电路及相关方法
公开(公告)号：US07190209B2
公开(公告)日：2007-03-13
申请号：US11119283
申请日：2005-04-28
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： G05F1/10
CPC分类号： H03K3/012 , H03K19/0016
摘要： An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.
摘要翻译：提供了一种集成电路，其包括具有第一PMOS晶体管和第一NMOS晶体管的多状态电路。在活动模式中，多状态电路可操作以在其中第一PMOS晶体管导通并且第一NMOS晶体管截止的第一状态和第一PMOS晶体管截止的第二状态之间切换，第一个NMOS晶体管导通。电源NMOS晶体管具有连接到电源电压端子的漏极，并且源极连接到第一PMOS晶体管的源极。电源PMOS晶体管具有连接到有效接地端子的漏极，并且源极连接到第一NMOS晶体管的源极。

9. 发明授权

US06946901B2 Low-power high-performance integrated circuit and related methods 有权
公开(公告)号：US06946901B2
公开(公告)日：2005-09-20
申请号：US10155490
申请日：2002-05-22
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K3/012 , H03K19/00 , G05F1/10
CPC分类号： H03K3/012 , H03K19/0016
摘要： An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

10. 发明申请

US20050201144A1 Low-power high-performance storage circuitry 审中-公开
公开(公告)号：US20050201144A1
公开(公告)日：2005-09-15
申请号：US11118938
申请日：2005-04-28
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K3/012 , H03K3/356 , H03K3/3565 , H03K19/00 , G11C11/00
CPC分类号： H03K3/3565 , G11C11/412 , G11C2207/2227 , H03K3/012 , H03K3/356156 , H03K19/0016
摘要： An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate coupled to a first access control node; and a second low threshold voltage access transistor including a first S/D coupled to the second data node and to the gate of the first PMOS transistor and to the gate of the first NMOS transistor and including a second S/D coupled to a second data access node and including a gate coupled to a second access control node.

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