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1. 发明申请

US20060038444A1 COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DISTRIBUTION NETWORK 失效
标题翻译：通信系统和使用微电子功率分配网络的方法
公开(公告)号：US20060038444A1
公开(公告)日：2006-02-23
申请号：US10711082
申请日：2004-08-20
申请人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
IPC分类号： H04B3/54 , G05B11/01
CPC分类号： H04B3/54 , H04B2203/5416
摘要： A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.
摘要翻译：一种通信系统，其包括具有配电网络的微电子芯片; 发射机，可操作地配置为产生通信信号并将所述通信信号提供给所述配电网络; 以及可操作地配置为从所述配电网接收所述通信信号的接收器。还提供了一种通过微电子芯片的配电网传送通信信号的方法。

2. 发明申请

US20060242524A1 SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION 失效
标题翻译：系统与片上互连验证的系统和方法
公开(公告)号：US20060242524A1
公开(公告)日：2006-10-26
申请号：US10906388
申请日：2005-02-17
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

3. 发明申请

US20070005290A1 METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE THROUGH DETERMINISTIC PATH DELAYS 失效
标题翻译：通过确定性延迟监测集成电路温度的方法和装置
公开(公告)号：US20070005290A1
公开(公告)日：2007-01-04
申请号：US11160601
申请日：2005-06-30
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Jason Norman , Stanley Stanski , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G01K1/00
CPC分类号： G01K3/14 , G01K3/10
摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.
摘要翻译：用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。

4. 发明申请

US20070006108A1 APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE LIBRARY ARCHITECTURE 有权
标题翻译：实现一体化电路IP核心图书馆架构的装置和方法
公开(公告)号：US20070006108A1
公开(公告)日：2007-01-04
申请号：US11160609
申请日：2005-06-30
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Stanley Stanski
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Stanley Stanski
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a communication structure included within the library.
摘要翻译：集成电路（IC）架构包括被配置为提供多个单独电路功能的知识产权（IP）核心库。所述IP核以与所述IP核中的各个IP核的定制功能选择相兼容的方式布置，其中通过包括在所述库内的通信结构来访问单独选择的核。

5. 发明申请

US20060041705A1 SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DEVICES IN SYSTEM ON CHIP ARCHITECTURES 审中-公开
标题翻译：芯片结构体系中共享外围核心器件之间的仲裁系统和方法
公开(公告)号：US20060041705A1
公开(公告)日：2006-02-23
申请号：US10711084
申请日：2004-08-20
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F2213/0038
摘要： A system for implementing arbitration between one or more shared peripheral core devices in system on chip (SOC) integrated circuit architecture includes a first microprocessor in communication with a first system bus, and a second microprocessor in communication with a second system bus. At least one peripheral core device is accessible by both the first microprocessor and said second microprocessor, and an arbitration unit is in communication with the first system bus and the second system bus. The arbitration unit is configured to control communication between the at least one peripheral core device and the first and second microprocessors.
摘要翻译：一种用于在系统级芯片（SOC）集成电路架构中的一个或多个共享外围核心装置之间实现仲裁的系统包括与第一系统总线通信的第一微处理器和与第二系统总线通信的第二微处理器。至少一个外围核心设备可由第一微处理器和所述第二微处理器访问，并且仲裁单元与第一系统总线和第二系统总线通信。仲裁单元被配置为控制至少一个外围核心设备与第一和第二微处理器之间的通信。

6. 发明申请

US20060095905A1 METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR SYSTEM 审中-公开
标题翻译：用于在多处理器系统中维护螺纹的方法和装置
公开(公告)号：US20060095905A1
公开(公告)日：2006-05-04
申请号：US10904259
申请日：2004-11-01
申请人： Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
发明人： Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A method for servicing threads within a multi-processor system is disclosed. In response to an input/output (I/O) request to a peripheral by a thread, a latency time is assigned to the thread such that the thread will not be interrogated until the latency time has lapsed. After the latency time is lapsed, a determination is made as to whether or not the I/O request has been responded. If the I/O request has not been responded after the latency time is lapsed, the latency time is assigned to the thread again. Otherwise, if the I/O request has been responded after the latency time is lapsed, the latency time is updated with an actual response time. The actual response time is from a time when the I/O request was made to a time when the I/O request was actually responded.
摘要翻译：公开了一种用于在多处理器系统内维护线程的方法。响应于线程对外设的输入/输出（I / O）请求，延迟时间被分配给线程，使得在延迟时间过去之前线程将不被询问。在延迟时间过去之后，确定I / O请求是否已被响应。如果延迟时间过后I / O请求未被响应，则延迟时间将再次分配给该线程。否则，如果在延迟时间过后已经响应了I / O请求，则延迟时间将以实际响应时间更新。实际的响应时间是从I / O请求到实际响应I / O请求时的时间。

7. 发明申请

US20070245290A1 METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-QUALIFIED EXPOSURE MASKS FOR SELECTED BLOCKS OF CIRCUITRY 失效
标题翻译：使用预先制作的集成电路的方法和用于选择的电路块的预先准许的接触掩模
公开(公告)号：US20070245290A1
公开(公告)日：2007-10-18
申请号：US11279666
申请日：2006-04-13
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/84
摘要： Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.
摘要翻译：公开了一种制造方法的实施例，其建立用于图案化满足已确定的性能和时序要求的不同电路块的预制和预先限定的掩模库。该方法的实施例使用多个掩模的步进曝光，包括从该库选择的至少一个掩模，以将芯片设计图案化到硅晶片上，其中芯片设计由两个或更多个互连的电路块组成。因此，对于给定的集成电路设计，可以从库中选择预制/预先限定的掩模，以对设计的一个，一些或所有电路块进行图案化。可选地，附加掩模可以被特别地制造并且被限定以在设计中对其他电路块（例如，应用专用逻辑）进行图案化。以这种方式图案化的电路块可通过通用或定制界面电连接，以完成芯片设计。

8. 发明申请

US20060262779A1 A METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN CORES IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于传输集成电路中的数据之间的数据的方法和装置
公开(公告)号：US20060262779A1
公开(公告)日：2006-11-23
申请号：US10908597
申请日：2005-05-18
申请人： Adam Courchesne , Kenneth Goodnow , W. Harding , David Milton , Jason Norman , Clarence Ogilvie , Jason Rotella , Paul Schanely , Sebastian Ventrone
发明人： Adam Courchesne , Kenneth Goodnow , W. Harding , David Milton , Jason Norman , Clarence Ogilvie , Jason Rotella , Paul Schanely , Sebastian Ventrone
IPC分类号： H04L12/50
CPC分类号： G06F15/7825
摘要： A method and apparatus for providing communication between various cores located in an integrated circuit. The method and apparatus uses Hubs/Routers to facilitate and manage communication of data from/between the cores according to a specified methodology.
摘要翻译：一种用于提供位于集成电路中的各种核心之间的通信的方法和装置。该方法和装置使用集线器/路由器来根据指定的方法来促进和管理来自/在核心之间的数据的通信。

9. 发明申请

US20080030226A1 FPGA POWERUP TO KNOWN FUNCTIONAL STATE 失效
标题翻译： FPGA电源到已知的功能状态
公开(公告)号：US20080030226A1
公开(公告)日：2008-02-07
申请号：US11869921
申请日：2007-10-10
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
IPC分类号： H03K19/173
CPC分类号： H03K19/17776 , H03K19/17732 , H03K19/17756 , H03K19/17772
摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.
摘要翻译：包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

10. 发明申请

US20070258305A1 DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
标题翻译：基于充电储存装置的可能性确定使用数据保留装置的相对数量
公开(公告)号：US20070258305A1
公开(公告)日：2007-11-08
申请号：US11279639
申请日：2006-04-13
申请人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Sebastian Ventrone , Keith Williams
发明人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Sebastian Ventrone , Keith Williams
IPC分类号： G11C7/00
CPC分类号： G06F12/121 , G06F12/122
摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
摘要翻译：公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

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