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1. 发明授权

US06506642B1 Removable spacer technique 有权
标题翻译：可拆卸间隔技术
公开(公告)号：US06506642B1
公开(公告)日：2003-01-14
申请号：US10020931
申请日：2001-12-19
申请人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
发明人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
IPC分类号： H01L218238
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6656
摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.
摘要翻译：亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物，在栅电极的已经被去除了第一侧壁间隔物的侧表面上。实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

2. 发明授权

US06720227B1 Method of forming source/drain regions in a semiconductor device 失效
标题翻译：在半导体器件中形成源/漏区的方法
公开(公告)号：US06720227B1
公开(公告)日：2004-04-13
申请号：US10059615
申请日：2002-01-29
申请人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
发明人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/7833
摘要： A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.
摘要翻译：提供了一种在半导体器件中形成源极/漏极区域的方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，通过至少执行以下步骤在衬底中邻近栅电极形成源极/漏极区：执行两个离子注入工艺以形成用于并且执行第三离子注入工艺以进一步形成用于该器件的源极/漏极区域。本发明可以使用各种N型和P型掺杂剂原子，例如砷，磷，硼和二氟化硼。

3. 发明授权

US06245649B1 Method for forming a retrograde impurity profile 有权
标题翻译：形成逆行杂质分布的方法
公开(公告)号：US06245649B1
公开(公告)日：2001-06-12
申请号：US09251923
申请日：1999-02-17
申请人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
发明人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L2104
CPC分类号： H01L29/105 , H01L21/2652
摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.
摘要翻译：提供了一种在半导体衬底中形成逆向杂质分布的方法。该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

4. 发明授权

US06787464B1 Method of forming silicide layers over a plurality of semiconductor devices 失效
标题翻译：在多个半导体器件上形成硅化物层的方法
公开(公告)号：US06787464B1
公开(公告)日：2004-09-07
申请号：US10189048
申请日：2002-07-02
申请人： Jon D. Cheek , Scott D. Luning
发明人： Jon D. Cheek , Scott D. Luning
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/823418 , H01L21/823443 , H01L21/823456 , H01L21/823814 , H01L21/823835 , H01L21/82385 , H01L29/7833
摘要： The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors. In yet another illustrative embodiment, the method comprises forming a layer of refractory metal to an original thickness above a plurality of transistors, reducing the original thickness of a portion of the layer of refractory metal above at least some of the transistors to define a layer of refractory metal having multiple thicknesses, and performing at least one anneal process to convert portions of the layer of refractory metal having multiple thicknesses to metal silicide regions on the transistors.
摘要翻译：本发明一般涉及基于栅极临界尺寸在晶体管上形成金属硅化物区域的各种方法。在一个说明性实施例中，该方法包括在多个晶体管上形成难熔金属层，减少至少部分晶体管的至少一部分难熔金属的厚度，并执行至少一个退火工艺以形成晶体管上方的金属硅化物区域。在另一示例性实施例中，该方法包括在多个晶体管上方形成难熔金属层，减小了具有栅极电极的第一晶体管之上的难熔金属层的厚度，临界尺寸小于临界尺寸的多个晶体管中的另一个晶体管的栅极电极结构，并且执行至少一个退火工艺以在所述多个晶体管上形成金属硅化物区域。在另一个说明性实施例中，该方法包括在多个晶体管上方形成原始厚度的难熔金属层，将难熔金属层的一部分的一部分的原始厚度减小到至少一些晶体管之上以限定一层具有多个厚度的难熔金属，并且执行至少一个退火工艺以将具有多个厚度的难熔金属层的部分转换成晶体管上的金属硅化物区域。

5. 发明授权

US06372587B1 Angled halo implant tailoring using implant mask 有权
标题翻译：使用植入物掩模的角度光晕植入物定制
公开(公告)号：US06372587B1
公开(公告)日：2002-04-16
申请号：US09568069
申请日：2000-05-10
申请人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
发明人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness &tgr; above the surface and having an edge disposed a distance &dgr; from the first edge of the structure. The method also includes implanting the halo implant at an angle &agr; with respect to a direction perpendicular to the surface, wherein the tangent of the angle &agr; is at least the ratio of the distance &dgr; to the thickness &tgr;.
摘要翻译：提供了一种用于在邻近结构的一侧的衬底中形成卤素注入的方法，所述方法包括在所述衬底的表面上方形成所述结构，所述结构具有第一和第二边缘并且形成限定邻近所述结构的区域的掩模，该面具具有厚度＆tgr; 并且具有与结构的第一边缘相距一定距离的边缘。该方法还包括将晕圈植入物相对于垂直于该表面的方向以角度α注入，其中角度α的切线至少为距离δ与厚度的比值。

6. 发明授权

US06566696B1 Self-aligned VT implant 有权
标题翻译：自对准VT植入
公开(公告)号：US06566696B1
公开(公告)日：2003-05-20
申请号：US09907359
申请日：2001-07-17
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L2980
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供了具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

7. 发明授权

US06274415B1 Self-aligned Vt implant 有权
标题翻译：自对准Vt植入物
公开(公告)号：US06274415B1
公开(公告)日：2001-08-14
申请号：US09489068
申请日：2000-01-21
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L21337
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

8. 发明授权

US06541321B1 Method of making transistors with gate insulation layers of differing thickness 有权
标题翻译：制造具有不同厚度的栅极绝缘层的晶体管的方法
公开(公告)号：US06541321B1
公开(公告)日：2003-04-01
申请号：US10145519
申请日：2002-05-14
申请人： James F. Buller , Jon D. Cheek
发明人： James F. Buller , Jon D. Cheek
IPC分类号： H01L21336
CPC分类号： H01L21/823462
摘要： In one illustrative embodiment, the method comprises forming a sacrificial layer of material above a substrate comprised of silicon, performing a wet etching process to remove the sacrificial layer, implanting fluorine atoms into selected portions of the substrate after the sacrificial layer is removed, and performing a thermal oxidation process to form a plurality of gate insulation layers above the substrate, the gate insulation layers formed above the fluorine implanted selected portions of the substrate having a thickness that is greater than a thickness of the gate insulation layers formed above portions of the substrate not implanted with fluorine.
摘要翻译：在一个说明性实施例中，该方法包括在由硅构成的衬底之上形成材料的牺牲层，执行湿蚀刻工艺以去除牺牲层，在去除牺牲层之后将氟原子注入到衬底的选定部分中，并执行热氧化工艺以在衬底上形成多个栅极绝缘层，形成在衬底的氟注入的选定部分上方的栅极绝缘层的厚度大于在衬底的上方形成的栅极绝缘层的厚度没有植入氟。

9. 发明授权

US5893739A Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer 失效
标题翻译：具有硼迁移势垒的非对称P沟道晶体管和选择性地形成的侧壁间隔物
公开(公告)号：US5893739A
公开(公告)日：1999-04-13
申请号：US720728
申请日：1996-10-01
申请人： Daniel Kadosh , Fred N. Hause , Jon D. Cheek
发明人： Daniel Kadosh , Fred N. Hause , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

10. 发明授权

US5852310A Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto 失效
标题翻译：具有图案化的上层晶体管衬底及其互连的多级晶体管制造方法
公开(公告)号：US5852310A
公开(公告)日：1998-12-22
申请号：US67793
申请日：1998-04-28
申请人： Daniel Kadosh , Mark I. Garnder , Jon D. Cheek
发明人： Daniel Kadosh , Mark I. Garnder , Jon D. Cheek
IPC分类号： H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L21/8221 , H01L23/485 , H01L23/535 , H01L27/0688 , H01L2924/0002
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同层次的器件之间的互连上。因此，引入了高性能互连，由此在一个晶体管级内的特征之间使互连尽可能短以达到另一晶体管级内的特征。互连使用直接在上级晶体管的阱与下部晶体管的阱之间布线的通孔，以便实现相应晶体管的阱之间的直接耦合。以这种方式的直接耦合使得排列在单独的高程水平上的晶体管的一致操作。通孔尽可能短，以减少衬底/阱电压电位的任何差异。这确保了在单独的高程水平上形成的晶体管的可预测的操作。

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