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1. 发明授权

US5950086A Method of fabricating an EPROM type device with reduced process residues 失效
标题翻译：制造具有减少的工艺残留物的EPROM型器件的方法
公开(公告)号：US5950086A
公开(公告)日：1999-09-07
申请号：US878119
申请日：1997-06-18
申请人： Satoshi Takahashi , Tatsuya Kajita , Hideo Kurihara , Hideki Komori , Masaaki Higashitani
发明人： Satoshi Takahashi , Tatsuya Kajita , Hideo Kurihara , Hideki Komori , Masaaki Higashitani
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/115
摘要： A semiconductor device is fabricated by the step of forming a first device isolation film in a peripheral circuit region by the use of a first pattern and a second device isolation film in a memory cell region by the use of a second pattern; forming a first conducting film processed by the use of a third pattern having a pattern-to-be-removed in a peripheral edge of the memory cell region; the step of forming an insulation film covering the memory cell region and processed by the use of a fourth pattern whose peripheral edge is positioned on the pattern-to-be-removed of the third pattern; and the step of forming a second conducting film processed by a fifth pattern.
摘要翻译：通过使用第二图案在存储单元区域中通过使用第一图案和第二器件隔离膜在外围电路区域中形成第一器件隔离膜的步骤来制造半导体器件; 形成通过使用在存储单元区域的外围边缘中具有要去除的图案的第三图案处理的第一导电膜; 形成覆盖存储单元区域并通过使用周边位于第三图案的图案上的第四图案进行处理的绝缘膜的步骤; 以及形成通过第五图案处理的第二导电膜的步骤。

2. 发明授权

US06579769B2 Semiconductor device manufacturing method including forming FOX with dual oxidation 有权
标题翻译：半导体器件制造方法，包括形成具有双重氧化的FOX
公开(公告)号：US06579769B2
公开(公告)日：2003-06-17
申请号：US09726384
申请日：2000-12-01
申请人： Hiroyuki Shimada , Masaaki Higashitani , Hideo Kurihara , Hideki Komori , Satoshi Takahashi
发明人： Hiroyuki Shimada , Masaaki Higashitani , Hideo Kurihara , Hideki Komori , Satoshi Takahashi
IPC分类号： H01L21336
CPC分类号： H01L21/76221
摘要： In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below the first window is enhanced. Accordingly, generation of projection on bird's beak of a selective oxide film can be prevented in a semiconductor device manufacturing method including a step of growing a local oxidation of silicon film.
摘要翻译：在制造半导体器件的方法中，包括在半导体衬底的表面上形成防氧化层的步骤，在氧化防止层中形成第一窗口，将半导体衬底放置在第一气氛中，其中氧气气体和第一量的氯气通过第一温度被供应，然后在第一温度下加热半导体衬底，使得通过热氧化从第一窗口暴露的半导体衬底的表面来生长第一选择性氧化物膜，形成第二通过图案化氧化防止层，并将半导体衬底放置在第二气氛中，在第二气氛中，将氧气和大于第一量的第二量的氯气供给到第二气氛中，然后在第二温度使得形成第二选择性氧化物膜，并且形成第一选择性氧化物膜的厚度增强了形成在第一窗口下方的氧化膜。因此，在包括生长硅膜的局部氧化的步骤的半导体器件制造方法中，可以防止在选择性氧化物膜的鸟嘴上产生投影。

3. 发明授权

US06187640B1 Semiconductor device manufacturing method including various oxidation steps with different concentration of chlorine to form a field oxide 有权
标题翻译：包括具有不同浓度的氯的各种氧化步骤以形成场氧化物的半导体器件制造方法
公开(公告)号：US06187640B1
公开(公告)日：2001-02-13
申请号：US09193252
申请日：1998-11-17
申请人： Hiroyuki Shimada , Masaaki Higashitani , Hideo Kurihara , Hideki Komori , Satoshi Takahashi
发明人： Hiroyuki Shimada , Masaaki Higashitani , Hideo Kurihara , Hideki Komori , Satoshi Takahashi
IPC分类号： H01L21336
CPC分类号： H01L21/76221
摘要： In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below the first window is enhanced. Accordingly, generation of projection on bird's beak of a selective oxide film can be prevented in a semiconductor device manufacturing method including a step of growing a local oxidation of silicon film.
摘要翻译：在制造半导体器件的方法中，包括在半导体衬底的表面上形成氧化防止层的步骤，在氧化防止层中形成第一窗口，将半导体衬底放置在第一气氛中，其中氧气并且在第一温度下通过第一量的氯气供应第一量的氯气，然后在第一温度下加热第一选择性氧化物膜，以便通过热氧化从第一窗口露出的半导体衬底的表面生长第一选择性氧化物膜，形成第二窗口通过图案化氧化防止层，并且将半导体衬底放置在第二气氛中，在第二气氛中，将氧气和大于第一量的第二量的氯气供给到第二气氛中，然后再次加热半导体衬底温度使得形成第二选择性氧化物膜，并且第一选择性氧化物膜的厚度在第一窗口下方形成的底片增强。因此，在包括生长硅膜的局部氧化的步骤的半导体器件制造方法中，可以防止在选择性氧化物膜的鸟嘴上产生投影。

4. 发明授权

US09390995B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09390995B2
公开(公告)日：2016-07-12
申请号：US14370803
申请日：2012-07-25
申请人： Kei Yamamoto , Kazuhiro Tada , Hideki Komori , Toru Kimura , Masaki Goto , Hiroyuki Yoshihara
发明人： Kei Yamamoto , Kazuhiro Tada , Hideki Komori , Toru Kimura , Masaki Goto , Hiroyuki Yoshihara
IPC分类号： H01L23/367 , H01L23/34 , B23P15/26 , H01L23/433 , H01L21/48 , H01L23/31 , H01L21/56 , H01L23/373 , H01L29/16 , H01L29/20
CPC分类号： H01L23/3672 , H01L21/4871 , H01L21/4882 , H01L21/56 , H01L21/565 , H01L23/3107 , H01L23/3735 , H01L23/4334 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins.
摘要翻译：目的在于提供一种鳍状集成型半导体器件及其制造方法，其具有简单的结构和良好的散热特性。半导体器件包括：在第一主面上形成有以直立状态排列的翅片的基板; 绝缘层，形成在所述基板的第二主面上，所述第二主面与所述基板的所述第一主面相对; 固定到所述绝缘层的电路图案; 以及连接到电路图案的半导体元件。翅片形成有沿翅片的厚度方向穿过的狭缝。

5. 发明授权

US06242305B1 Process for fabricating a bit-line using buried diffusion isolation 有权
标题翻译：使用掩埋扩散隔离制造位线的工艺
公开(公告)号：US06242305B1
公开(公告)日：2001-06-05
申请号：US09427404
申请日：1999-10-25
申请人： David K. Foote , Hideki Komori , Bharath Rangarajan , Fei Wang
发明人： David K. Foote , Hideki Komori , Bharath Rangarajan , Fei Wang
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure overlying the semiconductor substrate. Thereafter, a hard mask layer is formed to overlie ONO structure, the hard mask layer having an upper surface. To form a trench for the buried bit-line, an etch process is performed on the ONO structure. Thereafter, silicon dioxide is deposited to fill the trench. To control a thickness of the deposited silicon dioxide, a chemical-mechanical-polishing process is performed to planarize the silicon dioxide and form a planar surface continuous with the upper surface of the hard mask layer. Finally, the hard mask layer is removed and the remaining silicon dioxide forms a uniform bit-line oxide layer.
摘要翻译：制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成覆盖半导体衬底的ONO结构。此后，形成硬掩模层以覆盖ONO结构，硬掩模层具有上表面。为了形成掩埋位线的沟槽，对ONO结构进行蚀刻处理。此后，沉积二氧化硅以填充沟槽。为了控制沉积的二氧化硅的厚度，进行化学机械抛光工艺以使二氧化硅平坦化并形成与硬掩模层的上表面连续的平面。最后，去除硬掩模层，剩余的二氧化硅形成均匀的位线氧化物层。

6. 发明授权

US5770304A Wide bandwidth electromagnetic wave absorbing material 失效
标题翻译：宽带电磁波吸收材料
公开(公告)号：US5770304A
公开(公告)日：1998-06-23
申请号：US500836
申请日：1995-07-11
申请人： Koji Nakamura , Hideki Komori , Mitsuyuki Oda , Kazunori Kanda
发明人： Koji Nakamura , Hideki Komori , Mitsuyuki Oda , Kazunori Kanda
IPC分类号： H01Q17/00 , B32B5/16
CPC分类号： H01Q17/00 , H01Q17/004 , Y10S428/90 , Y10T428/256 , Y10T428/257 , Y10T428/258 , Y10T428/259 , Y10T428/26
摘要： The present invention provides a thin wide bandwidth electromagnetic wave absorbing material capable of absorbing electromagnetic waves in both the semi-microwave band and the semi-millimeter and millimeter wave band. The present electromagnetic wave absorbing material comprises: a first layer composed of a conductive material; a second layer comprising a particle of a metal oxide magnetic material and a matrix of a binder, being applied on the first layer; and a third layer comprising a particle of a metal magnetic material and a matrix of a binder, being applied on the second layer.
摘要翻译：本发明提供能够吸收半微波带和半毫米和毫米波段中的电磁波的薄宽带宽电磁波吸收材料。本电磁波吸收材料包括：由导电材料构成的第一层; 第二层，其包含金属氧化物磁性材料的颗粒和粘合剂的基体，施加在第一层上; 以及第三层，其包含金属磁性材料的颗粒和粘合剂的基体，施加在第二层上。

7. 发明申请

US20070117303A1 Semiconductor memory device (as amended) 有权
标题翻译：半导体存储器件（经修改）
公开(公告)号：US20070117303A1
公开(公告)日：2007-05-24
申请号：US11656438
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b）其浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的提高。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

8. 发明授权

US06713809B1 Dual bit memory device with isolated polysilicon floating gates 失效
标题翻译：具有隔离多晶硅浮动栅极的双位存储器件
公开(公告)号：US06713809B1
公开(公告)日：2004-03-30
申请号：US09809969
申请日：2001-03-16
申请人： Jusuke Ogura , Kazuhiro Kurihara , Masaru Yano , Hideki Komori , Tuan Pham , Angela Hui
发明人： Jusuke Ogura , Kazuhiro Kurihara , Masaru Yano , Hideki Komori , Tuan Pham , Angela Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0458 , H01L27/115 , H01L29/66825 , H01L29/7887
摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.
摘要翻译：本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。

9. 发明授权

US06573140B1 Process for making a dual bit memory device with isolated polysilicon floating gates 有权
标题翻译：制造具有隔离多晶硅浮动栅极的双位存储器件的工艺
公开(公告)号：US06573140B1
公开(公告)日：2003-06-03
申请号：US09810155
申请日：2001-03-16
申请人： Jusuke Ogura , Kiyoshi Izumi , Masaru Yano , Hideki Komori , Tuan Pham , Angela Hui
发明人： Jusuke Ogura , Kiyoshi Izumi , Masaru Yano , Hideki Komori , Tuan Pham , Angela Hui
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7887
摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.
摘要翻译：本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。还公开了用于制造根据本发明的存储器件的工艺。

10. 发明授权

US07227780B2 Semiconductor device and control method thereof 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07227780B2
公开(公告)日：2007-06-05
申请号：US11289997
申请日：2005-11-30
申请人： Hideki Komori , Shouichi Kawamura , Masanori Taya
发明人： Hideki Komori , Shouichi Kawamura , Masanori Taya
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C2216/14
摘要： A semiconductor device including a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, a detection circuit that refers to an output voltage of the program voltage supply circuit and detects a decrease of the program voltage supplied thereby, a frequency converting circuit that generates the clock signal by converting a frequency of a clock signal generated by an oscillator circuit into a lower frequency when the program voltage supplied by the program voltage supply circuit becomes equal to or lower than a given voltage, and a voltage generating circuit that generates a voltage supplied to a gate of the memory cell by using a clock signal, the frequency of which is converted by the frequency converting circuit. It is therefore possible to make the best use of the ability of the program voltage generating circuit in programming.
摘要翻译：一种半导体器件，包括：向存储单元的漏极供给编程电压的编程电压供给电路;参考编程电压供给电路的输出电压并检测由此提供的编程电压的降低的检测电路;频率转换电路，当由编程电压供应电路提供的编程电压变为等于或低于给定电压时，通过将由振荡器电路产生的时钟信号的频率转换为较低频率来产生时钟信号;以及电压产生电路其通过使用频率由频率转换电路转换的时钟信号来产生提供给存储器单元的栅极的电压。因此，可以充分利用编程电压产生电路在编程中的能力。

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