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1. 发明申请

US20090327981A1 Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged 审中-公开
标题翻译：半导体器件或印刷线路板设计方法和设计支持系统，通过使用表示在封装时发生的寄生元件的半导体器件模型来实现设置
公开(公告)号：US20090327981A1
公开(公告)日：2009-12-31
申请号：US12457930
申请日：2009-06-25
申请人： Satoshi Nakamura , Tsutomu Hara , Mitsuaki Katagiri , Yukitoshi Hirose , Satoshi Itaya , Ken Iwakura
发明人： Satoshi Nakamura , Tsutomu Hara , Mitsuaki Katagiri , Yukitoshi Hirose , Satoshi Itaya , Ken Iwakura
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78 , H05K1/181 , H05K3/0005
摘要： Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.
摘要翻译：获取校正电路模型，用于校正在电路板上安装时变化的电特性参数。校正电路模型被添加到单独的模型中，该模型表示隔离的单独的半导体器件以产生表示板安装状态的半导体器件的半导体器件模型。表示调整对象系统的等效电路模型连接到所创建的半导体器件模型，并且基于与等效电路模型相连接的半导体器件模型，与调整对象系统相关的调整对象值为计算。将这些调整对象值与预先确定的限制值进行比较，并且基于比较结果，确定调整对象系统的设计指南。

2. 发明申请

US20080072194A1 METHOD FOR DESIGNING DEVICE, SYSTEM FOR AIDING TO DESIGN DEVICE, AND COMPUTER PROGRAM PRODUCT THEREFOR 失效
标题翻译：用于设计设备的方法，用于设计设备的系统，以及计算机程序产品
公开(公告)号：US20080072194A1
公开(公告)日：2008-03-20
申请号：US11854591
申请日：2007-09-13
申请人： Mitsuaki KATAGIRI , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
发明人： Mitsuaki KATAGIRI , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。第二半导体芯片包括耦合到输入焊盘的输出焊盘。调整对象被连接到第一和第二半导体芯片。主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

3. 发明授权

US07681154B2 Method for designing device, system for aiding to design device, and computer program product therefor 失效
标题翻译：设计装置的方法，辅助设计装置的系统及其计算机程序产品
公开(公告)号：US07681154B2
公开(公告)日：2010-03-16
申请号：US11854591
申请日：2007-09-13
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。第二半导体芯片包括耦合到输入焊盘的输出焊盘。调整对象被连接到第一和第二半导体芯片。主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

4. 发明授权

US07694245B2 Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor 失效
标题翻译：半导体封装设计方法，半导体封装设计系统及其计算机程序产品
公开(公告)号：US07694245B2
公开(公告)日：2010-04-06
申请号：US11710965
申请日：2007-02-27
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/50 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。选择第一和第二目标变量之一作为主要目标变量。比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

5. 发明申请

US20070204251A1 Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor 失效
标题翻译：半导体封装设计方法，半导体封装设计系统及其计算机程序产品
公开(公告)号：US20070204251A1
公开(公告)日：2007-08-30
申请号：US11710965
申请日：2007-02-27
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/50 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。选择第一和第二目标变量之一作为主要目标变量。比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

6. 发明授权

US08243465B2 Semiconductor device with additional power supply paths 失效
标题翻译：具有附加电源路径的半导体器件
公开(公告)号：US08243465B2
公开(公告)日：2012-08-14
申请号：US12707996
申请日：2010-02-18
申请人： Satoshi Itaya , Satoshi Isa , Mitsuaki Katagiri , Dai Sasaki
发明人： Satoshi Itaya , Satoshi Isa , Mitsuaki Katagiri , Dai Sasaki
IPC分类号： H01R9/00 , H01L23/02
CPC分类号： H05K1/181 , G11C5/063 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2924/00014 , H01L2924/0102 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.
摘要翻译：在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

7. 发明授权

US07569428B2 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US07569428B2
公开(公告)日：2009-08-04
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L21/82 , H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

8. 发明申请

US20070069362A1 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US20070069362A1
公开(公告)日：2007-03-29
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

9. 发明申请

US20110084385A1 Semiconductor device and information processing system including the same 有权
标题翻译：半导体装置和信息处理系统也包括在内
公开(公告)号：US20110084385A1
公开(公告)日：2011-04-14
申请号：US12923789
申请日：2010-10-07
申请人： Satoshi Itaya , Kayoko Shibata , Shoji Azuma , Akira Ide
发明人： Satoshi Itaya , Kayoko Shibata , Shoji Azuma , Akira Ide
IPC分类号： H01L23/485
CPC分类号： H01L21/76898 , H01L21/563 , H01L23/3128 , H01L23/481 , H01L23/49811 , H01L24/03 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13022 , H01L2224/1308 , H01L2224/13082 , H01L2224/13099 , H01L2224/1403 , H01L2224/16145 , H01L2224/73203 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01051 , H01L2924/01055 , H01L2924/01074 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014
摘要： A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.
摘要翻译：半导体器件包括多个核心芯片和控制芯片芯片的接口芯片。芯片芯片和接口芯片中的每一个都包括穿透半导体衬底的多个穿过硅通孔和分别连接到通孔硅通孔的多个焊盘。贯通硅通孔包括供电电源电位或接地电位的电源系统的贯穿硅通孔，以及供给各种信号的信号系统的通孔硅通孔。在焊盘中，连接到电源系统的贯穿硅通孔的焊盘的至少一个尺寸大于连接到信号系统的通过硅通孔的焊盘的尺寸。因此，可以确保更大的寄生电容。

10. 发明申请

US20110311257A1 IMAGE FORMING APPARATUS, CONTROL METHOD, AND RECORDING MEDIUM 有权
标题翻译：图像形成装置，控制方法和记录介质
公开(公告)号：US20110311257A1
公开(公告)日：2011-12-22
申请号：US13164095
申请日：2011-06-20
申请人： Taizo Nozawa , Yukio Futamata , Noboru Furuyama , Satoshi Itaya , Hiroshi Katakura , Setsuo Takada
发明人： Taizo Nozawa , Yukio Futamata , Noboru Furuyama , Satoshi Itaya , Hiroshi Katakura , Setsuo Takada
IPC分类号： G03G15/20
CPC分类号： G03G15/2078 , G03G15/2039
摘要： An embodiment provides an image forming apparatus including: a job acquiring unit that acquires an image forming job that gives instructions for performing forming of an image; an image forming process control unit that controls performance of the image forming job that the job acquiring unit acquires; a temperature information acquiring unit that acquires information showing temperature of the heating rotary body; a determining unit that determines whether the temperature of the heating rotary body which is acquired by the temperature information acquiring unit is equal to or higher than a predetermined stand-by temperature set as a temperature in a stand-by state that stands by to perform the image forming process, when the image forming process is completed, based on the image forming job by the image forming process control unit; and a fixing device control unit, which controls the fixing device, performs a first stand-by control process that increases the temperature of the heating rotary body to the stand-by temperature by heating the heating rotary body with the heating member while rotating the heating rotary body with the heating rotary body and the pressing body in contact, when the determining unit determines that the temperature of the heating rotary body is lower than the stand-by temperature. Further, the fixing device control unit stops the rotation of the heating rotary body and performs a second stand-by control process that makes the fixing device stand by, without heating the heating rotary body with the heating member, when the determining unit determines that the temperature of the heating rotary body is the stand-by temperature or higher.
摘要翻译：实施例提供了一种图像形成装置，包括：作业获取单元，其获取给出用于执行图像形成的指令的图像形成作业; 图像形成处理控制单元，其控制作业获取单元获取的图像形成作业的性能; 温度信息获取单元，其获取表示所述加热旋转体的温度的信息; 确定单元，其确定由所述温度信息获取单元获取的所述加热旋转体的温度是否等于或高于设置为待机状态下的待执行状态的预定待机温度图像形成处理，当图像形成处理完成时，基于图像形成处理控制单元的图像形成作业; 以及控制定影装置的定影装置控制单元，进行第一待机控制处理，其通过在加热部件的同时加热加热旋转体而使加热旋转体的温度升高到待机温度当确定单元确定加热旋转体的温度低于待机温度时，加热旋转体的旋转体和压制体接触。此外，定影装置控制单元停止加热旋转体的旋转，并且当确定单元确定了加热旋转体的旋转时，执行使定影装置待机的第二待机控制处理，而不加热加热旋转体，加热旋转体的温度为待机温度或更高。

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