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1. 发明授权

US07681154B2 Method for designing device, system for aiding to design device, and computer program product therefor 失效
标题翻译：设计装置的方法，辅助设计装置的系统及其计算机程序产品
公开(公告)号：US07681154B2
公开(公告)日：2010-03-16
申请号：US11854591
申请日：2007-09-13
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。第二半导体芯片包括耦合到输入焊盘的输出焊盘。调整对象被连接到第一和第二半导体芯片。主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

2. 发明申请

US20080072194A1 METHOD FOR DESIGNING DEVICE, SYSTEM FOR AIDING TO DESIGN DEVICE, AND COMPUTER PROGRAM PRODUCT THEREFOR 失效
标题翻译：用于设计设备的方法，用于设计设备的系统，以及计算机程序产品
公开(公告)号：US20080072194A1
公开(公告)日：2008-03-20
申请号：US11854591
申请日：2007-09-13
申请人： Mitsuaki KATAGIRI , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
发明人： Mitsuaki KATAGIRI , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。第二半导体芯片包括耦合到输入焊盘的输出焊盘。调整对象被连接到第一和第二半导体芯片。主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

3. 发明申请

US20070033553A1 Inductance analysis system and method and program therefor 有权
标题翻译：电感分析系统及其方法和程序
公开(公告)号：US20070033553A1
公开(公告)日：2007-02-08
申请号：US11495711
申请日：2006-07-31
申请人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
发明人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H05K1/115 , H05K3/0005
摘要： System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal current is placed in the vicinity of a signal through-hole on the power supply plane, based on position information of said signal through-hole, is received. Potential distribution in the power supply plane is determined and output. The non-coupled inductance from the signal through-hole to the power supply through-hole in the power supply plane is evaluated. In the potential analysis, non-coupled inductance L from the signal through-hole to the power supply through-hole is represented by resistance R. The relationship that a voltage increment ΔV is represented by the product of the non-coupled inductance L and the rate of time change of the current, ΔV=LΔI/Δt, is replaced by the relationship that the voltage V is represented by the product of resistance R and non-coupled current I, V=R×I. Potential analysis is performed by analyzing two-dimensional heat diffusion in the power supply plane assuming that a heat source is placed at a beginning point of the non-coupled current.
摘要翻译：用于电感分析的系统，方法和程序，用于减少分析时间，以应对系统尺寸的增加，在分析中达到高精度。基于所述电源平面的位置信息，在电源平面的信息通过孔附近，在电源平面附近的信号通孔附近设置电源面的信息，信号通孔，被接收。确定并输出电源平面中的电位分布。评估从信号通孔到电源平面中电源通孔的非耦合电感。在电位分析中，由电阻R表示从信号通孔到电源通孔的非耦合电感L.电压增量DeltaV由非耦合电感L和电流的时间变化DeltaV = LDeltaI / Deltat由电压R和非耦合电流I，V = RxI的乘积表示的电压代替。假设热源位于非耦合电流的起始点，通过分析供电平面中的二维热扩散来执行潜在分析。

4. 发明授权

US07823096B2 Inductance analysis system and method and program therefor 有权
标题翻译：电感分析系统及其方法和程序
公开(公告)号：US07823096B2
公开(公告)日：2010-10-26
申请号：US11495711
申请日：2006-07-31
申请人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
发明人： Mitsuaki Katagiri , Takashi Iida , Hiroya Shimizu , Satoshi Isa
IPC分类号： G06F17/50 , H01L23/52
CPC分类号： G06F17/5036 , H05K1/115 , H05K3/0005
摘要： System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal current is placed in the vicinity of a signal through-hole on the power supply plane, based on position information of said signal through-hole, is received. Potential distribution in the power supply plane is determined and output. The non-coupled inductance from the signal through-hole to the power supply through-hole in the power supply plane is evaluated. In the potential analysis, non-coupled inductance L from the signal through-hole to the power supply through-hole is represented by resistance R. The relationship that a voltage increment ΔV is represented by the product of the non-coupled inductance L and the rate of time change of the current, ΔV=LΔI/Δt, is replaced by the relationship that the voltage V is represented by the product of resistance R and non-coupled current I, V=R×I. Potential analysis is performed by analyzing two-dimensional heat diffusion in the power supply plane assuming that a heat source is placed at a beginning point of the non-coupled current.
摘要翻译：用于电感分析的系统，方法和程序，用于减少分析时间，以应对系统尺寸的增加，在分析中达到高精度。基于所述电源平面的位置信息，在电源平面的信息通过孔附近，在电源平面附近的信号通孔附近设置电源面的信息，信号通孔，被接收。确定并输出电源平面中的电位分布。评估从信号通孔到电源平面中电源通孔的非耦合电感。在电位分析中，由电阻R表示从信号通孔到电源通孔的非耦合电感L.电压增量与Dgr，V之间的关系由非耦合电感L 并且电流的时间变化率＆Dgr; V = L＆Dgr; I /＆Dgr; t被替换为电压V由非电阻R和非耦合电流I的乘积表示的关系，V = R× 一世。假设热源位于非耦合电流的起始点，通过分析供电平面中的二维热扩散来执行潜在分析。

5. 发明授权

US08362614B2 Fine pitch grid array type semiconductor device 有权
标题翻译：细间距阵列型半导体器件
公开(公告)号：US08362614B2
公开(公告)日：2013-01-29
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.
摘要翻译：半导体器件具有其中布置有多个半导体部件和多个焊盘的半导体芯片，布置在栅格中的多个外部连接触点，以及用于电连接焊盘和外部连接触点的多条引线。焊盘包括多个焊盘组，其包括连接到共同的多个半导体部件的一对电极焊盘和分别连接到连接到电极焊盘的半导体部件的多个信号焊盘。在每个焊盘组中，每个信号焊盘被布置成与电极焊盘之一相邻; 并且从每个信号焊盘延伸的每条焊丝沿着与每个信号焊盘相邻的电极焊盘延伸的焊丝延伸。

6. 发明授权

US07345892B2 Semiconductor device, noise reduction method, and shield cover 失效
标题翻译：半导体器件，降噪方法和屏蔽罩
公开(公告)号：US07345892B2
公开(公告)日：2008-03-18
申请号：US11134132
申请日：2005-05-20
申请人： Masaharu Imazato , Atsushi Nakamura , Takayuki Watanabe , Kensuke Tsuneda , Mitsuaki Katagiri , Hiroya Shimizu , Tatsuya Nagata
发明人： Masaharu Imazato , Atsushi Nakamura , Takayuki Watanabe , Kensuke Tsuneda , Mitsuaki Katagiri , Hiroya Shimizu , Tatsuya Nagata
IPC分类号： H09K9/00
CPC分类号： G11C5/04 , H05K1/0218 , H05K9/0064
摘要： In a memory module, reference potential connecting patterns are disposed on high frequency signal lines and/or on the extension lines extending from the terminal ends of the signal lines as well as a shield cover for covering semiconductor memory chips is disposed on the substrate, and the reference potential connecting patterns are connected to the shield cover through metal cover contact parts.
摘要翻译：在存储器模块中，参考电位连接图案设置在高频信号线上和/或从信号线的末端延伸的延长线上，并且用于覆盖半导体存储器芯片的屏蔽盖设置在基板上，以及参考电位连接图案通过金属盖接触部分连接到屏蔽罩。

7. 发明申请

US20060081972A1 Fine pitch grid array type semiconductor device 有权
公开(公告)号：US20060081972A1
公开(公告)日：2006-04-20
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

8. 发明申请

US20050270758A1 Semiconductor device, noise reduction method, and shield cover 失效
标题翻译：半导体器件，降噪方法和屏蔽罩
公开(公告)号：US20050270758A1
公开(公告)日：2005-12-08
申请号：US11134132
申请日：2005-05-20
申请人： Masaharu Imazato , Atsushi Nakamura , Takayuki Watanabe , Kensuke Tsuneda , Mitsuaki Katagiri , Hiroya Shimizu , Tatsuya Nagata
发明人： Masaharu Imazato , Atsushi Nakamura , Takayuki Watanabe , Kensuke Tsuneda , Mitsuaki Katagiri , Hiroya Shimizu , Tatsuya Nagata
IPC分类号： H05K9/00 , G11C5/00 , H01L23/00 , H05K1/02
CPC分类号： G11C5/04 , H05K1/0218 , H05K9/0064
摘要： In a memory module, reference potential connecting patterns are disposed on high frequency signal lines and/or on the extension lines extending from the terminal ends of the signal lines as well as a shield cover for covering semiconductor memory chips is disposed on the substrate, and the reference potential connecting patterns are connected to the shield cover through metal cover contact parts.
摘要翻译：在存储器模块中，参考电位连接图案设置在高频信号线上和/或从信号线的末端延伸的延长线上，并且用于覆盖半导体存储器芯片的屏蔽盖设置在基板上，以及参考电位连接图案通过金属盖接触部分连接到屏蔽罩。

9. 发明授权

US06211576B1 Semiconductor device 有权
公开(公告)号：US06211576B1
公开(公告)日：2001-04-03
申请号：US09397853
申请日：1999-09-17
申请人： Hiroya Shimizu , Asao Nishimura , Tosiho Miyamoto , Hideki Tanaka , Hideo Miura
发明人： Hiroya Shimizu , Asao Nishimura , Tosiho Miyamoto , Hideki Tanaka , Hideo Miura
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/50 , H01L23/5286 , H01L23/552 , H01L23/645 , H01L23/66 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

10. 发明授权

US5838549A Memory module and an IC card 失效
标题翻译：内存模块和IC卡
公开(公告)号：US5838549A
公开(公告)日：1998-11-17
申请号：US788423
申请日：1997-01-27
申请人： Tatsuya Nagata , Hiroya Shimizu , Atsushi Nakamura , Hideshi Fukumoto , Toshio Sugano
发明人： Tatsuya Nagata , Hiroya Shimizu , Atsushi Nakamura , Hideshi Fukumoto , Toshio Sugano
IPC分类号： H05K3/46 , H01L27/10 , H05K1/02 , H05K1/11 , H05K3/42 , H01R9/09
CPC分类号： H05K1/117 , H01R12/721 , H05K1/0216 , H01R23/6873 , H05K1/0224 , H05K2201/0191 , H05K2201/09327 , H05K2201/09336 , H05K2201/09481 , H05K2201/09681 , H05K2201/0969 , H05K2201/10159 , H05K2201/10689 , H05K3/429 , Y10S439/941
摘要： In semiconductor modules having a plurality of semiconductor devices mounted on a multilayer printed circuit boards as the processing speed increases, a short circuit current flowing through CMOS devices in the semiconductor devices during operation can cause noise because of ground inductance or power supply inductance. This noise can result in erroneous operations. To solve this problem, the power supply layer or grand layer that is connected to either the power supply terminal Vcc or the ground terminal Gnd of each semiconductor memory, which is located farther from the connection terminals, is arranged closer to the semiconductor memories with this arrangement, the short circuit current flowing through the semiconductor memories is more strongly magnetically coupled with the power supply layer or ground layer arranged close to them. Thus, it is possible to reduce the effective inductance. This, in turn, reduces noise, making it possible to provide a semiconductor module with an increased processing speed.
摘要翻译：在处理速度增加时，具有安装在多层印刷电路板上的多个半导体器件的半导体模块中，在工作期间流过半导体器件中的CMOS器件的短路电流可能由于接地电感或电源电感而引起噪声。这种噪音可能导致错误的操作。为了解决这个问题，连接到距连接端子更远的每个半导体存储器的电源端子Vcc或接地端子Gnd的电源层或者大层被布置成更靠近半导体存储器布置时，流过半导体存储器的短路电流与靠近它们布置的电源层或接地层更牢固地磁耦合。因此，可以降低有效电感。这反过来降低了噪声，使得可以提供具有增加的处理速度的半导体模块。

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