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1. 发明授权

US07694245B2 Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor 失效
标题翻译：半导体封装设计方法，半导体封装设计系统及其计算机程序产品
公开(公告)号：US07694245B2
公开(公告)日：2010-04-06
申请号：US11710965
申请日：2007-02-27
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/50 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。选择第一和第二目标变量之一作为主要目标变量。比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

2. 发明申请

US20070204251A1 Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor 失效
标题翻译：半导体封装设计方法，半导体封装设计系统及其计算机程序产品
公开(公告)号：US20070204251A1
公开(公告)日：2007-08-30
申请号：US11710965
申请日：2007-02-27
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/50 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。选择第一和第二目标变量之一作为主要目标变量。比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

3. 发明授权

US07689944B2 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US07689944B2
公开(公告)日：2010-03-30
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

4. 发明申请

US20070057380A1 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US20070057380A1
公开(公告)日：2007-03-15
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： H01L23/48
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

5. 发明授权

US06977832B2 Semiconductor memory device capable of improving quality of voltage waveform given in a signal interconnection layer 有权
标题翻译：能够提高信号互连层中给出的电压波形的质量的半导体存储器件
公开(公告)号：US06977832B2
公开(公告)日：2005-12-20
申请号：US10329293
申请日：2002-12-24
申请人： Satoshi Isa , Yoji Nishio
发明人： Satoshi Isa , Yoji Nishio
IPC分类号： G11C11/41 , G06F12/00 , G11C5/00 , G11C5/06 , G11C5/14 , G11C11/401 , H01L21/82 , H01L21/822 , H01L27/04 , G11C5/02
CPC分类号： G11C5/14 , G11C5/063
摘要： In a multilayer interconnection layer of a mother board and a memory module, a position relationship between a bus interconnection layer and a conductive layer of a power supply layer or a ground layer opposite to the bus interconnection layer is substantially held in not only the mother board but also the memory module and a relationship of multilayer interconnections is unified. As a result, it is possible to reduce disturbance of a return current of a high frequency signal given to the bus interconnection layer, to prevent degradation of quality of a signal waveform caused by the disturbance of the return current, and to prevent unnecessary electromagnetic waves from radiating caused by the disturbance of the return current. When a position relationship between the bus interconnection layer and an opposite conductive layer is not held at a constant, a similar effect is obtained by disposing a bypass capacitor in the vicinity of a portion where a plane of the bus interconnection layer and the conductive layer is switched.
摘要翻译：在母板和存储器模块的多层互连层中，总线互连层与电源层或与母线互连层相对的接地层的导电层之间的位置关系基本上不仅保持在母板而且内存模块和多层互连的关系是统一的。结果，可以减少给予总线互连层的高频信号的返回电流的干扰，以防止由于返回电流的干扰导致的信号波形的质量劣化，并且防止不必要的电磁波由辐射引起的回波电流的干扰。当总线互连层和相对导电层之间的位置关系不保持恒定时，通过在总线互连层和导电层的平面的部分附近设置旁路电容器来获得类似的效果切换

6. 发明申请

US20100321060A1 SEMICONDUCTOR LSI AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体LSI和半导体器件
公开(公告)号：US20100321060A1
公开(公告)日：2010-12-23
申请号：US12816684
申请日：2010-06-16
申请人： Yoji Nishio , Yutaka Uematsu , Hideki Oosaka , Akihiro Namba , Satoshi Nakamura
发明人： Yoji Nishio , Yutaka Uematsu , Hideki Oosaka , Akihiro Namba , Satoshi Nakamura
IPC分类号： H03K19/003
CPC分类号： H03K19/003
摘要： In a signal transmission system, performing signal transmission via signal interconnections 4-1 to 4-3 between a memory 1 and a memory controller 2 mounted on a printed circuit board 3, noise or jitter may tend to be increased in the memory 1 and in the memory controller 2 at a specified data rate due to interconnection length resonance. Registers 6-1 and 6-2 are provided to hold information on the data rate. These registers 6-1 and 6-2 are provided in the signal transmission system along with a control system that modifies the relationship between clock frequency and interconnection length. The data rate or the propagation delay time is controlled to allow for avoiding the resonance.
摘要翻译：在信号传输系统中，通过安装在印刷电路板3上的存储器1和存储器控制器2之间的信号互连4-1至4-3执行信号传输，在存储器1中可能倾向于增加噪声或抖动存储器控制器2由于互连长度共振而以指定的数据速率。提供寄存器6-1和6-2以保存关于数据速率的信息。这些寄存器6-1和6-2与调制时钟频率和互连长度之间的关系的控制系统一起提供在信号传输系统中。控制数据速率或传播延迟时间以避免共振。

7. 发明授权

US08922029B2 Apparatus having a wiring board and memory devices 有权
标题翻译：具有接线板和存储器件的设备
公开(公告)号：US08922029B2
公开(公告)日：2014-12-30
申请号：US13363396
申请日：2012-02-01
申请人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , G11C5/06 , G11C5/04 , G11C8/14 , H05K1/18
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译：具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

8. 发明申请

US20110109361A1 Semiconductor device and information processing system 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：US20110109361A1
公开(公告)日：2011-05-12
申请号：US12926255
申请日：2010-11-04
申请人： Yoji Nishio
发明人： Yoji Nishio
IPC分类号： H03K5/12
CPC分类号： H03K19/00384 , H03K19/00361
摘要： The semiconductor device includes an output driver and a characteristic switching circuit that switches characteristics of the output driver. The characteristic switching circuit mutually matches a rising time and a falling time of an output signal output from the output driver, when a power voltage supplied to a power line is a first voltage, with a rising time and a falling time of the output signal output from the output driver, when the power voltage supplied to the power line is a second voltage. As a result, an increase in an influence of a harmonic component or a crosstalk when the power voltage is reduced does not occur. Moreover, because a receiving condition on a receiver side does not change even when the power voltage is reduced, signal transmission and reception can be performed correctly irrespective of the power voltage.
摘要翻译：半导体器件包括输出驱动器和切换输出驱动器的特性的特征切换电路。当提供给电力线的电源电压是第一电压时，特性切换电路相互匹配从输出驱动器输出的输出信号的上升时间和下降时间，输出信号输出的上升时间和下降时间当输出驱动器提供给电力线的电源电压是第二电压时。结果，不会发生电力电压降低时的谐波成分或串扰的影响的增加。此外，由于即使电源电压降低，接收机侧的接收状态也不变化，所以无论电源电压如何，都可以正确地进行信号的发送和接收。

9. 发明申请

US20110093764A1 MEMORY MODULE ON WHICH REGULAR CHIPS AND ERROR CORRECTION CHIPS ARE MOUNTED 有权
标题翻译：常规电池和错误校正电池的存储器模块安装
公开(公告)号：US20110093764A1
公开(公告)日：2011-04-21
申请号：US12908512
申请日：2010-10-20
申请人： Wataru TSUKADA , Shiro Harashima , Yoji Nishio
发明人： Wataru TSUKADA , Shiro Harashima , Yoji Nishio
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044 , H03M13/13
摘要： Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.
摘要翻译：将其中存储用户数据的常规芯片封装和存储其中的纠错码的纠错芯片封装安装在模块基板上。模块基板在X方向上具有不同坐标的第一和第二安装区域，并且第二安装区域具有不同Y坐标的第三和第四安装区域。常规包装件相对地布置在模块基板的表面和背面上的第一安装区域中。纠错芯片封装相对地布置在模块基板的表面和背面上的第三安装区域中。缓冲用户数据和纠错码的存储器缓冲器布置在第四安装区域中。

10. 发明授权

US07411806B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07411806B2
公开(公告)日：2008-08-12
申请号：US11634405
申请日：2006-12-06
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

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