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1. 发明授权

US08395412B2 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US08395412B2
公开(公告)日：2013-03-12
申请号：US13067644
申请日：2011-06-16
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.
摘要翻译：一种方法包括发出校准命令并响应于校准命令执行校准操作。校准操作包括通过更新第一代码来调整第一副本缓冲器的阻抗，第一复制缓冲器在电路配置中基本上与包括在输出缓冲器中的上拉和下拉电路中的一个相同，调整第二代阻抗具有更新第二代码的副本缓冲器，所述第二复制缓冲器在电路配置中与包括在所述输出缓冲器中的所述上拉和下拉电路中的另一个基本相同，当所述阻抗的第一复制缓冲器达到第一电平，并且当第二复制缓冲器的阻抗达到第二电平时，控制第二锁存电路以保持第二代码。

2. 发明申请

US20100312956A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312956A1
公开(公告)日：2010-12-09
申请号：US12801325
申请日：2010-06-03
申请人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
发明人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1057 , G11C7/1084 , H01L2224/48091 , H01L2224/48227 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。至少两个存储器芯片被分配给每个数据寄存器缓冲器。每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

3. 发明授权

US07847377B2 Semiconductor device including semiconductor chip with two pad rows 有权
标题翻译：半导体器件包括具有两个焊盘行的半导体芯片
公开(公告)号：US07847377B2
公开(公告)日：2010-12-07
申请号：US11528688
申请日：2006-09-28
申请人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
发明人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L27/07
CPC分类号： H01L23/50 , H01L23/49838 , H01L23/4985 , H01L24/06 , H01L2224/05554
摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
摘要翻译：半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。封装基板结合到半导体芯片。封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。桥接部分设置在基板开口上方以相互连接第一和第二布线区域。球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。

4. 发明申请

US20100097096A1 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US20100097096A1
公开(公告)日：2010-04-22
申请号：US12654253
申请日：2009-12-15
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.
摘要翻译：调整输出缓冲器的阻抗水平的半导体器件包括复制缓冲电路，其包括与输出缓冲器基本相同的电路配置，计数器电路改变阻抗代码以改变副本缓冲器的阻抗电平;锁存电路暂时保持响应于控制信号的阻抗代码，以及响应于从校准命令的发布而经过预定时间段而产生控制信号的终止确定电路，而不管复制缓冲器尚未达到期望的事实阻抗水平。

5. 发明授权

US07391113B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07391113B2
公开(公告)日：2008-06-24
申请号：US11391449
申请日：2006-03-29
申请人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
发明人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
摘要翻译：公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感的半导体芯片。焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

6. 发明申请

US20070075440A1 Semiconductor device including semiconductor chip with two pad rows 有权
标题翻译：半导体器件包括具有两个焊盘行的半导体芯片
公开(公告)号：US20070075440A1
公开(公告)日：2007-04-05
申请号：US11528688
申请日：2006-09-28
申请人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
发明人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L23/4985 , H01L24/06 , H01L2224/05554
摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
摘要翻译：半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。封装基板结合到半导体芯片。封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。桥接部分设置在基板开口上方以相互连接第一和第二布线区域。球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。

7. 发明申请

US20060081972A1 Fine pitch grid array type semiconductor device 有权
公开(公告)号：US20060081972A1
公开(公告)日：2006-04-20
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

8. 发明授权

US08362614B2 Fine pitch grid array type semiconductor device 有权
标题翻译：细间距阵列型半导体器件
公开(公告)号：US08362614B2
公开(公告)日：2013-01-29
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.
摘要翻译：半导体器件具有其中布置有多个半导体部件和多个焊盘的半导体芯片，布置在栅格中的多个外部连接触点，以及用于电连接焊盘和外部连接触点的多条引线。焊盘包括多个焊盘组，其包括连接到共同的多个半导体部件的一对电极焊盘和分别连接到连接到电极焊盘的半导体部件的多个信号焊盘。在每个焊盘组中，每个信号焊盘被布置成与电极焊盘之一相邻; 并且从每个信号焊盘延伸的每条焊丝沿着与每个信号焊盘相邻的电极焊盘延伸的焊丝延伸。

9. 发明申请

US20110248742A1 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US20110248742A1
公开(公告)日：2011-10-13
申请号：US13067644
申请日：2011-06-16
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.
摘要翻译：一种方法包括发出校准命令并响应于校准命令执行校准操作。校准操作包括通过更新第一代码来调整第一副本缓冲器的阻抗，第一复制缓冲器在电路配置中基本上与包括在输出缓冲器中的上拉和下拉电路中的一个相同，调整第二代阻抗具有更新第二代码的副本缓冲器，所述第二复制缓冲器在电路配置中与包括在所述输出缓冲器中的所述上拉和下拉电路中的另一个基本相同，当所述阻抗的第一复制缓冲器达到第一电平，并且当第二复制缓冲器的阻抗达到第二电平时，控制第二锁存电路以保持第二代码。

10. 发明申请

US20100309706A1 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US20100309706A1
公开(公告)日：2010-12-09
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

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