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1. 发明申请

US20060123142A1 Method and apparatus for providing peer-to-peer data transfer within a computing environment 有权
标题翻译：用于在计算环境内提供对等数据传输的方法和装置
公开(公告)号：US20060123142A1
公开(公告)日：2006-06-08
申请号：US11005150
申请日：2004-12-06
申请人： Samuel Duncan , Wei-Je Huang , John Edmondson
发明人： Samuel Duncan , Wei-Je Huang , John Edmondson
IPC分类号： G06F3/00
CPC分类号： H04L12/66
摘要： A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.
摘要翻译：一种用于通过互连结构提供对等数据传输的方法和装置。该方法和装置使得第一设备能够通过在互连结构上传递读取和写入请求来向/从第二设备的本地存储器读取和/或写入数据。即使当互连结构的通信协议不允许这样的传输时，也可以执行这种数据传送。

2. 发明申请

US20060120376A1 Method and apparatus for providing peer-to-peer data transfer within a computing environment 有权
公开(公告)号：US20060120376A1
公开(公告)日：2006-06-08
申请号：US11005451
申请日：2004-12-06
申请人： Samuel Duncan , Wei-Je Huang , John Edmondson
发明人： Samuel Duncan , Wei-Je Huang , John Edmondson
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9073
摘要： A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.

3. 发明授权

US08244984B1 System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy 有权
标题翻译：使用依赖于数据类的驱逐策略来清理中间缓存中的脏数据的系统和方法
公开(公告)号：US08244984B1
公开(公告)日：2012-08-14
申请号：US12330467
申请日：2008-12-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John Edmondson
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John Edmondson
IPC分类号： G06F13/00 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0897 , G06F12/126 , G06F2212/301 , G06F2212/302
摘要： In one embodiment, a method for managing information related to dirty data stored in an intermediate cache coupled to one or more clients and to an external memory includes receiving a dirty data notification related to dirty data residing in the intermediate cache, the dirty data notification including a memory address indicating a location in the external memory where the dirty data should be stored and a data type associated with the dirty data, and extracting a bank page number from the memory address that identifies a bank page within the external memory where the dirty data should be stored. The embodiment also includes incrementing a first count associated with a first entry in a notification sorter that is affirmatively associated with the bank page, determining that the dirty data has a first data type, and incrementing a second count associated with the first entry.
摘要翻译：在一个实施例中，用于管理与存储在耦合到一个或多个客户端和外部存储器的中间高速缓存中的脏数据有关的信息的方法包括接收与驻留在中间高速缓存中的脏数据相关的脏数据通知，该脏数据通知包括指示外部存储器中应该存储脏数据的位置的存储器地址和与脏数据相关联的数据类型，以及从识别外部存储器内的存储器页面的存储器地址提取存储体页号，其中脏数据应该存储。该实施例还包括增加与肯定与银行页面相关联的通知分类器中的与第一条目相关联的第一计数，确定脏数据具有第一数据类型，并递增与第一条目相关联的第二计数。

4. 发明申请

US20070263757A1 Digital clock recovery circuit 审中-公开
公开(公告)号：US20070263757A1
公开(公告)日：2007-11-15
申请号：US11879689
申请日：2007-07-18
申请人： William Dally , John Edmondson , Ramin Farjad-Rad
发明人： William Dally , John Edmondson , Ramin Farjad-Rad
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03L7/0814 , H03L7/089 , H03L7/091 , H03L7/093 , H04L7/0025 , H04L7/0337 , Y10S331/02
摘要： A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

5. 发明授权

US5680544A Method for testing an on-chip cache for repair 失效
标题翻译：用于测试片上缓存进行修复的方法
公开(公告)号：US5680544A
公开(公告)日：1997-10-21
申请号：US523297
申请日：1995-09-05
申请人： John Edmondson , Scott Taylor
发明人： John Edmondson , Scott Taylor
IPC分类号： G06F11/267 , G11C29/34 , G11C29/38 , G11C29/44 , G11C29/56 , G11C29/00
CPC分类号： G11C29/56 , G11C29/34 , G11C29/44 , G06F11/2236 , G11C29/38
摘要： A test system is provided which tests the on chip cache of a microprocessor (CPU). The test system provides test vectors to the CPU in a specified sequences. The CPU then uses its internal general purpose registers to write the vectors the cache memory locations. After writing, the data is read back and compared to an expected value. The results are then stored in other general purpose registers of the CPU. Using the CPUs general purpose registers to record the test results allows the test system to test many cache locations in parallel. Furthermore the test system allows the test to proceed in a fixed number of CPU clock cycles regardless of any detected errors.
摘要翻译：提供了测试微处理器（CPU）的片上高速缓存的测试系统。测试系统以指定的顺序向CPU提供测试向量。 CPU然后使用其内部通用寄存器来写入高速缓冲存储器位置的向量。写入后，数据将被读回并与预期值进行比较。然后将结果存储在CPU的其他通用寄存器中。使用CPU通用寄存器来记录测试结果允许测试系统并行测试许多高速缓存位置。此外，测试系统允许测试以固定数量的CPU时钟周期进行，而不管任何检测到的错误。

6. 发明授权

US07111155B1 Digital signal processor computation core with input operand selection from operand bus for dual operations 有权
标题翻译：数字信号处理器计算核心，具有来自操作数总线的输入操作数选择，用于双操作
公开(公告)号：US07111155B1
公开(公告)日：2006-09-19
申请号：US09570108
申请日：2000-05-12
申请人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman , Russell L. Rivin
发明人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman , Russell L. Rivin
IPC分类号： G06F7/38
CPC分类号： G06F9/3867 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/30149 , G06F9/3824 , G06F9/3885
摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
摘要翻译：计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。计算块包括寄存器文件和双执行单元。执行单元包括用于在执行数字信号计算时增强性能的特征。计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。有限脉冲响应滤波算法在双执行单元上实现了高性能。

7. 发明授权

US5317720A Processor system with writeback cache using writeback and non writeback transactions stored in separate queues 失效
标题翻译：具有回写高速缓存的处理器系统使用存储在单独队列中的回写和非回写事务
公开(公告)号：US5317720A
公开(公告)日：1994-05-31
申请号：US34581
申请日：1993-03-22
申请人： Rebecca L. Stamm , John Edmondson , David Archer , Samyojita Nadkarni , Raymond Strouble
发明人： Rebecca L. Stamm , John Edmondson , David Archer , Samyojita Nadkarni , Raymond Strouble
IPC分类号： G06F9/32 , F02B75/02 , G06F9/38 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0831 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , F02B2075/025
摘要： A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.
摘要翻译：执行可变长度指令的流水线CPU，并使用各种数据宽度引用存储器。在分层高速缓存布置中使用回写高速缓存（而不是写通），并且即使由于队列已满而抑制其他访问，也允许回写。提供单独的队列用于来自存储器的返回数据，并且高速缓存无效，但是顺序或总线事务由指针排列来维护。 CPU与系统总线通信使用的总线协议是挂起类型，由总线标识的总线标识的总线上的事务，总线授权的仲裁与总线上的地址/数据事务同时进行。

8. 发明授权

US08365015B1 Memory-based error recovery 有权
标题翻译：基于内存的错误恢复
公开(公告)号：US08365015B1
公开(公告)日：2013-01-29
申请号：US12853121
申请日：2010-08-09
申请人： Shu-Yi Yu , Shane Keil , John Edmondson
发明人： Shu-Yi Yu , Shane Keil , John Edmondson
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G06F9/3863
摘要： The present disclosure provides memory level error correction methods and apparatus. A memory controller is intermediate the memory devices, such as DRAM chips or memory modules, and a processor, such a graphics processor or a main processor. The memory controller can provide error correction. In an example, the memory controller includes a buffer to store instructions and data for execution by the controller and a replay buffer to store the instructions such that operations can be replayed to prior state before the error. An error detector receives data read from the memory devices and if no error is detected outputs the data. If an error is detected, the error detector signals the memory controller to replay the instructions stored in the replay buffer.
摘要翻译：本公开提供了存储器级错误校正方法和装置。存储器控制器在诸如DRAM芯片或存储器模块的存储器件之间，以及诸如图形处理器或主处理器的处理器之间。存储器控制器可以提供纠错。在一个示例中，存储器控制器包括一个缓冲器，用于存储用于由控制器执行的指令和数据以及重放缓冲器来存储指令，使得可以在错误之前将操作重播到先前的状态。错误检测器接收从存储器件读取的数据，如果没有检测到错误则输出数据。如果检测到错误，则错误检测器通知存储器控制器重放存储在重放缓冲器中的指令。

9. 发明授权

US06859872B1 Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation 有权
标题翻译：数字信号处理器计算核心，具有存储器访问级的管线和用于有效操作的多个累积级
公开(公告)号：US06859872B1
公开(公告)日：2005-02-22
申请号：US09570213
申请日：2000-05-12
申请人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman
发明人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3867 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/381 , G06F9/3824 , G06F9/3826
摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
摘要翻译：计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。计算块包括寄存器文件和双执行单元。执行单元包括用于在执行数字信号计算时增强性能的特征。计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。有限脉冲响应滤波算法在双执行单元上实现了高性能。

10. 发明授权

US06820189B1 Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation 有权
标题翻译：计算核心执行多个操作DSP指令和较短长度的微控制器指令，无需执行开关操作
公开(公告)号：US06820189B1
公开(公告)日：2004-11-16
申请号：US09570094
申请日：2000-05-12
申请人： Marc Hoffman , John Edmondson , Jose Fridman
发明人： Marc Hoffman , John Edmondson , Jose Fridman
IPC分类号： G06F930
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/30149 , G06F9/3824 , G06F9/3867
摘要： A computation core for executing programmed instructions includes an execution block for performing digital signal processor operations in response to digital signal processor instructions and for performing microcontroller operations in response to microcontroller instructions, a register file for storing operands for and results of the digital signal processor operations and the microcontroller operations, and control logic for providing control signals to the execution block and the register file in response to the instructions. The digital signal processor instructions each have a first length and the microcontroller instructions each have a second length that is less than the first length.
摘要翻译：用于执行编程指令的计算核心包括用于响应于数字信号处理器指令执行数字信号处理器操作并响应于微控制器指令执行微控制器操作的执行块，用于存储数字信号处理器操作的操作数和结果的寄存器文件和微控制器操作，以及用于响应于指令向执行块和寄存器文件提供控制信号的控制逻辑。数字信号处理器指令各自具有第一长度，并且微控制器指令各自具有小于第一长度的第二长度。

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