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1. 发明授权

US5317720A Processor system with writeback cache using writeback and non writeback transactions stored in separate queues 失效
标题翻译：具有回写高速缓存的处理器系统使用存储在单独队列中的回写和非回写事务
公开(公告)号：US5317720A
公开(公告)日：1994-05-31
申请号：US34581
申请日：1993-03-22
申请人： Rebecca L. Stamm , John Edmondson , David Archer , Samyojita Nadkarni , Raymond Strouble
发明人： Rebecca L. Stamm , John Edmondson , David Archer , Samyojita Nadkarni , Raymond Strouble
IPC分类号： G06F9/32 , F02B75/02 , G06F9/38 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0831 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , F02B2075/025
摘要： A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.
摘要翻译：执行可变长度指令的流水线CPU，并使用各种数据宽度引用存储器。在分层高速缓存布置中使用回写高速缓存（而不是写通），并且即使由于队列已满而抑制其他访问，也允许回写。提供单独的队列用于来自存储器的返回数据，并且高速缓存无效，但是顺序或总线事务由指针排列来维护。 CPU与系统总线通信使用的总线协议是挂起类型，由总线标识的总线标识的总线上的事务，总线授权的仲裁与总线上的地址/数据事务同时进行。

2. 发明授权

US5155843A Error transition mode for multi-processor system 失效
标题翻译：多处理器系统的错误转换模式
公开(公告)号：US5155843A
公开(公告)日：1992-10-13
申请号：US547597
申请日：1990-06-29
申请人： Rebecca L. Stamm , R. Iris Bahar , Michael Callander , Linda Chao , Derrick R. Meyer , Douglas Sanders , Richard L. Sites , Raymond Strouble , Nicholas Wade
发明人： Rebecca L. Stamm , R. Iris Bahar , Michael Callander , Linda Chao , Derrick R. Meyer , Douglas Sanders , Richard L. Sites , Raymond Strouble , Nicholas Wade
IPC分类号： F02B75/02 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0815 , F02B2075/025
摘要： A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency. For CAL type instructions, a method for determining which registers need to be saved is executed in a minimum number of cycles, examining groups of register mask bits at one time. Internal processor registers are accessed with short (byte width) addresses instead of full physical addresses as used for memory and I/O references, but off-chip processor registers are memory-mapped and accessed by the same busses using the same controls as the memory and I/O. In a non-recoverable error detected by ECC circuits in the cache, an error transition mode is entered wherein the cache operates under limited access rules, allowing a maximum of access by the system for data blocks owned by the cache, but yet minimizing changes to the cache data so that diagnostics may be run. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

3. 发明授权

US06049901A Test system for integrated circuits using a single memory for both the parallel and scan modes of testing 失效
标题翻译：使用单个存储器进行并行和扫描测试模式的集成电路测试系统
公开(公告)号：US06049901A
公开(公告)日：2000-04-11
申请号：US931164
申请日：1997-09-16
申请人： Mary C. Stock , Raymond Strouble , Ernest P. Walker
发明人： Mary C. Stock , Raymond Strouble , Ernest P. Walker
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319
CPC分类号： G01R31/31919
摘要： A semiconductor test system has a scan test mode and a parallel test mode. A single memory using substantially all of its storage space stores a) parallel test vectors for use during the parallel test mode, and b) parallel test vectors and scan test vectors for use during the scan test mode. A switch is used to change from the parallel test mode to the scan test mode. A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode. The speed of the scan test mode is increased by interleaving the memory and reading test vectors out of the memory in parallel. Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT). Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.
摘要翻译：半导体测试系统具有扫描测试模式和并行测试模式。使用其基本上所有存储空间的单个存储器存储a）在并行测试模式期间使用的并行测试向量，以及b）在扫描测试模式期间使用的并行测试向量和扫描测试向量。开关用于从并行测试模式切换到扫描测试模式。耦合到单个存储器的模式发生器操纵在并行测试模式期间使用的并行测试向量以及在扫描测试模式期间使用的并行和扫描测试向量。扫描测试模式的速度通过交错存储器并将测试矢量并行读出存储器来增加。通过创建多个扫描链并将其应用于被测器件（DUT）的多个引脚，进一步降低处理时间。最后，通过将正被传送到总线的扫描链数据进行多路复用，将馈送扫描链数据的总线的时钟速度增加到DUT的引脚。

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