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1. 发明授权

US07111155B1 Digital signal processor computation core with input operand selection from operand bus for dual operations 有权
标题翻译：数字信号处理器计算核心，具有来自操作数总线的输入操作数选择，用于双操作
公开(公告)号：US07111155B1
公开(公告)日：2006-09-19
申请号：US09570108
申请日：2000-05-12
申请人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman , Russell L. Rivin
发明人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman , Russell L. Rivin
IPC分类号： G06F7/38
CPC分类号： G06F9/3867 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/30149 , G06F9/3824 , G06F9/3885
摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
摘要翻译：计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。计算块包括寄存器文件和双执行单元。执行单元包括用于在执行数字信号计算时增强性能的特征。计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。有限脉冲响应滤波算法在双执行单元上实现了高性能。

2. 发明授权

US06859872B1 Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation 有权
标题翻译：数字信号处理器计算核心，具有存储器访问级的管线和用于有效操作的多个累积级
公开(公告)号：US06859872B1
公开(公告)日：2005-02-22
申请号：US09570213
申请日：2000-05-12
申请人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman
发明人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3867 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/381 , G06F9/3824 , G06F9/3826
摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
摘要翻译：计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。计算块包括寄存器文件和双执行单元。执行单元包括用于在执行数字信号计算时增强性能的特征。计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。有限脉冲响应滤波算法在双执行单元上实现了高性能。

3. 发明授权

US06820189B1 Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation 有权
标题翻译：计算核心执行多个操作DSP指令和较短长度的微控制器指令，无需执行开关操作
公开(公告)号：US06820189B1
公开(公告)日：2004-11-16
申请号：US09570094
申请日：2000-05-12
申请人： Marc Hoffman , John Edmondson , Jose Fridman
发明人： Marc Hoffman , John Edmondson , Jose Fridman
IPC分类号： G06F930
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/30149 , G06F9/3824 , G06F9/3867
摘要： A computation core for executing programmed instructions includes an execution block for performing digital signal processor operations in response to digital signal processor instructions and for performing microcontroller operations in response to microcontroller instructions, a register file for storing operands for and results of the digital signal processor operations and the microcontroller operations, and control logic for providing control signals to the execution block and the register file in response to the instructions. The digital signal processor instructions each have a first length and the microcontroller instructions each have a second length that is less than the first length.
摘要翻译：用于执行编程指令的计算核心包括用于响应于数字信号处理器指令执行数字信号处理器操作并响应于微控制器指令执行微控制器操作的执行块，用于存储数字信号处理器操作的操作数和结果的寄存器文件和微控制器操作，以及用于响应于指令向执行块和寄存器文件提供控制信号的控制逻辑。数字信号处理器指令各自具有第一长度，并且微控制器指令各自具有小于第一长度的第二长度。

4. 发明授权

US07062523B1 Method for efficiently computing a fast fourier transform 有权
标题翻译：用于有效计算快速傅里叶变换的方法
公开(公告)号：US07062523B1
公开(公告)日：2006-06-13
申请号：US09630258
申请日：2000-08-01
申请人： Marc Hoffman , Jose Fridman
发明人： Marc Hoffman , Jose Fridman
IPC分类号： G06F15/00
CPC分类号： G06F17/142
摘要： A method for computing an out of place FFT in which each stage of the FFT has an identical signal flow geometry. In each stage of the presently disclosed FFT method the group loop has been eliminated, the twiddle factor data is stored in bit-reversed manner, and the output data values are stored with a unity stride.
摘要翻译：一种计算不合格FFT的方法，其中FFT的每一级具有相同的信号流几何形状。在目前公开的FFT方法的每个阶段中，组循环已被消除，旋转因子数据以位反转的方式存储，并且以单位步幅存储输出数据值。

5. 发明授权

US06898690B2 Multi-tiered memory bank having different data buffer sizes with a programmable bank select 有权
标题翻译：具有不同数据缓冲区大小的多层存储体，具有可编程存储区选择
公开(公告)号：US06898690B2
公开(公告)日：2005-05-24
申请号：US10639020
申请日：2003-08-11
申请人： Hebbalalu S. Ramagopal , Michael Allen , Jose Fridman , Marc Hoffman
发明人： Hebbalalu S. Ramagopal , Michael Allen , Jose Fridman , Marc Hoffman
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0802 , G06F12/0846 , G06F2212/2515
摘要： An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.
摘要翻译：公开了一种具有核心处理器和多个高速缓冲存储器组的装置。高速缓冲存储器组以这样的方式连接到核心处理器，以便为所述核心处理器提供基本同时的数据访问。

6. 发明授权

US06606684B1 Multi-tiered memory bank having different data buffer sizes with a programmable bank select 有权
标题翻译：具有不同数据缓冲区大小的多层存储体，具有可编程存储区选择
公开(公告)号：US06606684B1
公开(公告)日：2003-08-12
申请号：US09541114
申请日：2000-03-31
申请人： Hebbalalu S. Ramagopal , Michael Allen , Jose Fridman , Marc Hoffman
发明人： Hebbalalu S. Ramagopal , Michael Allen , Jose Fridman , Marc Hoffman
IPC分类号： G06F1210
CPC分类号： G06F12/0802 , G06F12/0846 , G06F2212/2515
摘要： An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.
摘要翻译：公开了一种具有核心处理器和多个高速缓冲存储器组的装置。高速缓冲存储器组以这样的方式连接到核心处理器，以便为所述核心处理器提供基本同时的数据访问。

7. 发明授权

US07107302B1 Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units 有权
标题翻译：用于在具有双执行单元的数字信号处理器上实现的有限脉冲响应滤波器算法
公开(公告)号：US07107302B1
公开(公告)日：2006-09-12
申请号：US09570847
申请日：2000-05-12
申请人： Jose Fridman , Marc Hoffman
发明人： Jose Fridman , Marc Hoffman
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , H03H17/06 , H03H2218/10
摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
摘要翻译：计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。计算块包括寄存器文件和双执行单元。执行单元包括用于在执行数字信号计算时增强性能的特征。计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。有限脉冲响应滤波算法在双执行单元上实现了高性能。

8. 发明授权

US06771271B2 Apparatus and method of processing image data 有权
标题翻译：处理图像数据的装置和方法
公开(公告)号：US06771271B2
公开(公告)日：2004-08-03
申请号：US10170604
申请日：2002-06-13
申请人： Ke Ning , Marc Hoffman , Gabby Yi
发明人： Ke Ning , Marc Hoffman , Gabby Yi
IPC分类号： G06F1300
CPC分类号： G06T1/60
摘要： A relatively high speed circular memory device, in combination with other processes, improves image processing efficiency. To that end, a method and apparatus of processing image data stored in an initial memory logically divides the image into a plurality of contiguous strips. A first plurality of the strips are stored in a working memory having a circular addressing arrangement, where the working memory is faster than the initial memory and has a plurality of sequential address locations. The first plurality of strips are contiguous and have a start address. In addition, the first plurality of strips are stored in the working memory in a contiguous manner, and processed through the working memory relative to the start address.
摘要翻译：与其他工艺相结合的相对高速的圆形存储器件提高了图像处理效率。为此，将存储在初始存储器中的图像数据进行处理的方法和装置将图像逻辑地划分成多个连续的条带。第一组多个条被存储在具有圆形寻址布置的工作存储器中，其中工作存储器比初始存储器快，并且具有多个顺序地址位置。第一组多个条带是连续的并且具有起始地址。此外，第一多个条以连续的方式存储在工作存储器中，并且通过工作存储器相对于起始地址进行处理。

9. 发明授权

US06356162B1 Impedance compensation for a cable and connector 有权
标题翻译：电缆和连接器的阻抗补偿
公开(公告)号：US06356162B1
公开(公告)日：2002-03-12
申请号：US09286113
申请日：1999-04-02
申请人： Yves DeFlandre , Marc Hoffman , Gary Cyr
发明人： Yves DeFlandre , Marc Hoffman , Gary Cyr
IPC分类号： H01P500
CPC分类号： H03H7/383
摘要： In an interconnection system including a cable and connectors, compensation is provided for stray reactances found in the connector elements. The connector elements may be RJ-style connector plug and jack pairs, which exhibit characteristic capacitive and inductive properties. The compensation is capacitive and/or inductive elements formed in the cable, components of the connectors, or an external printed wiring board. A double &pgr;-network is the preferred circuit topology for the compensated system.
摘要翻译：在包括电缆和连接器的互连系统中，为连接器元件中发现的杂散电抗提供补偿。连接器元件可以是RJ型连接器插头和插座对，其具有特征的电容和电感特性。补偿是形成在电缆中的电容和/或电感元件，连接器的部件或外部印刷线路板。双pi网络是补偿系统的优选电路拓扑。

10. 发明授权

US08406303B2 Motion estimation using prediction guided decimated search 有权
标题翻译：运动估计使用预测指导抽取搜索
公开(公告)号：US08406303B2
公开(公告)日：2013-03-26
申请号：US11638838
申请日：2006-12-14
申请人： Marc Hoffman , Wei Zhang , Raka Singh , Ke Ning
发明人： Marc Hoffman , Wei Zhang , Raka Singh , Ke Ning
IPC分类号： H04N11/04
CPC分类号： H04N19/57 , G06T7/223 , H04N19/523 , H04N19/533 , H04N19/557 , H04N19/56
摘要： A method and apparatus utilizing a prediction guided decimated search motion estimation algorithm are provided. The prediction guided decimated search motion estimation algorithm generates a motion vector used to encode a macroblock in a frame from a video sequence. The algorithm includes generating full-pixel seed vectors, performing a full-pixel search around the generated seed vectors, which is followed by a fractional pixel search. The full-pixel seed vectors generated are a predicted motion vector and a hierarchical motion vector. A fractional pixel search may be conducted around a final motion vector generated by the full-pixel search and may include a half-pixel search and a quarter-pixel search. The prediction guided decimated search motion estimation algorithm can be implemented in both software and hardware. The algorithm is characterized by improved efficiency, scalability, and decreased complexity.
摘要翻译：提供了利用预测引导抽取搜索运动估计算法的方法和装置。预测引导抽取搜索运动估计算法生成用于对来自视频序列的帧中的宏块进行编码的运动矢量。该算法包括生成全像素种子矢量，围绕生成的种子矢量执行全像素搜索，其后跟分数像素搜索。生成的全像素种子矢量是预测运动矢量和分层运动矢量。可以围绕由全像素搜索生成的最终运动矢量进行分数像素搜索，并且可以包括半像素搜索和四分之一像素搜索。预测引导的抽取搜索运动估计算法可以在软件和硬件两个方面实现。该算法的特征在于提高效率，可扩展性和降低的复杂性。

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