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    • 1. 发明授权
      US09002693B2 Wire like link for cycle reproducible and cycle accurate hardware accelerator 有权
    • Wire like link for cycle reproducible and cycle accurate hardware accelerator
    • 线条链接循环可再现和循环精确的硬件加速器
    • US09002693B2
    • 2015-04-07
    • US13342128
    • 2012-01-02
    • Sameh Asaad , Mohit Kapur , Benjamin D. Parker
    • Sameh Asaad , Mohit Kapur , Benjamin D. Parker
    • G06F17/50
    • G06F17/5027
    • First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
    • 提供了第一和第二现场可编程门阵列，其实现要被模拟的电路设计的第一和第二块。 现场可编程门阵列以第一时钟频率操作，并且提供线状链路以在它们之间发送多个信号。 线状链路包括在第一现场可编程门阵列上串行化串行化多个信号的串行器; 第二现场可编程门阵列上的解串器，用于反序列化所述多个信号; 以及序列化器和解串器之间的连接。 串行器和解串器以大于第一时钟频率的第二时钟频率操作，并且选择第二时钟频率使得多个信号的发送和接收的延迟小于对应于第一时钟频率的周期 。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明申请
      US20130170525A1 WIRE LIKE LINK FOR CYCLE REPRODUCIBLE AND CYCLE ACCURATE HARDWARE ACCELERATOR 有权
    • WIRE LIKE LINK FOR CYCLE REPRODUCIBLE AND CYCLE ACCURATE HARDWARE ACCELERATOR
    • 绕线循环可循环硬件加速器
    • US20130170525A1
    • 2013-07-04
    • US13342128
    • 2012-01-02
    • Sameh Asaad , Mohit Kapur , Benjamin D. Parker
    • Sameh Asaad , Mohit Kapur , Benjamin D. Parker
    • H04B1/38
    • G06F17/5027
    • First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
    • 提供了第一和第二现场可编程门阵列，其实现要被仿真的电路设计的第一和第二块。 现场可编程门阵列以第一时钟频率操作，并且提供线状链路以在它们之间发送多个信号。 线状链路包括在第一现场可编程门阵列上串行化串行化多个信号的串行器; 第二现场可编程门阵列上的解串器，用于反序列化所述多个信号; 以及序列化器和解串器之间的连接。 串行器和解串器以大于第一时钟频率的第二时钟频率操作，并且选择第二时钟频率使得多个信号的发送和接收的延迟小于对应于第一时钟频率的周期 。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US08737233B2 Increasing throughput of multiplexed electrical bus in pipe-lined architecture 有权
    • Increasing throughput of multiplexed electrical bus in pipe-lined architecture
    • 在管道结构中提高复用电气总线的吞吐量
    • US08737233B2
    • 2014-05-27
    • US13236109
    • 2011-09-19
    • Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
    • Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
    • H04L12/26 , H04L12/28 , H04L12/16 , H04L12/66
    • H04L12/2602 , G06F13/4059 , H04L12/28 , H04L12/66 , H04L43/00
    • Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
    • 公开了通过利用计算机或其他系统的可用流水线级来增加多路复用电母线的吞吐量的技术。 例如，用于增加连接系统中的至少两个设备的电气总线的吞吐量的方法包括在两个设备中的一个信号接收中引入至少一个信号保持级，使得两个 操作设备不受信号从两个设备中的信号传输一个传播到两个设备中的信号接收设备之一所需的电气总线的工作频率的周期数量的限制。 优选地，引入到两个装置中的信号接收装置之一中的信号保持级是从两个装置中的信号发送装置之一重新分配的流水线级。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20130070606A1 INCREASING THROUGHPUT OF MULTIPLEXED ELECTRICAL BUS IN PIPE-LINED ARCHITECTURE 有权
    • INCREASING THROUGHPUT OF MULTIPLEXED ELECTRICAL BUS IN PIPE-LINED ARCHITECTURE
    • 管道式建筑中多路电气总线的增加
    • US20130070606A1
    • 2013-03-21
    • US13236109
    • 2011-09-19
    • Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
    • Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
    • H04L12/66 , H04L12/26
    • H04L12/2602 , G06F13/4059 , H04L12/28 , H04L12/66 , H04L43/00
    • Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
    • 公开了通过利用计算机或其他系统的可用流水线级来增加多路复用电母线的吞吐量的技术。 例如，用于增加连接系统中的至少两个设备的电气总线的吞吐量的方法包括在两个设备中的一个信号接收中引入至少一个信号保持级，使得两个 操作设备不受信号从两个设备中的信号传输一个传播到两个设备中的信号接收设备之一所需的电气总线的工作频率的周期数量的限制。 优选地，引入到两个装置中的信号接收装置之一中的信号保持级是从两个装置中的信号发送装置之一重新分配的流水线级。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US07051186B2 Selective bypassing of a multi-port register file 失效
    • Selective bypassing of a multi-port register file
    • 选择性绕过多端口寄存器文件
    • US07051186B2
    • 2006-05-23
    • US10230492
    • 2002-08-29
    • Sameh Asaad , Jaime H. Moreno , Victor Zyuban
    • Sameh Asaad , Jaime H. Moreno , Victor Zyuban
    • G06F15/82 , G06F9/305
    • G06F9/3826 , G06F9/30109
    • A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.
    • 可以选择性地旁路多端口寄存器文件，使得当在跟随生成的相同索引中在后续操作中请求元素时，结果向量中的任何元素被绕过到后续操作的输入向量的相同索引。 或者，当动态组成向量的N个要素作为下一个操作的输入被精确地按照它们被生成的相同顺序被请求作为输入时，放置在寄存器文件中的结果可以被绕过到后续的操作。 也就是说，为了绕过，N个向量元素被视为单个实体。 类似的规则适用于直通路径。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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