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1. 发明授权

US5053849A Transistor with overlapping gate/drain and two-layered gate structures 失效
标题翻译：具有重叠栅极/漏极和双层栅极结构的晶体管
公开(公告)号：US5053849A
公开(公告)日：1991-10-01
申请号：US515659
申请日：1990-04-25
申请人： Ryuichi Izawa , Tokuo Kure , Shimpei Iijima , Eiji Takeda , Yasuo Igura , Akemi Hamada , Atsushi Hiraiwa
发明人： Ryuichi Izawa , Tokuo Kure , Shimpei Iijima , Eiji Takeda , Yasuo Igura , Akemi Hamada , Atsushi Hiraiwa
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/6659 , H01L29/42376 , H01L29/4916 , H01L29/4925
摘要： Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.
摘要翻译：这里公开的是高密度的半导体器件。具有高密度和微结构的半导体器件即使在低电源电压下也需要具有高击穿电压和高速度。半导体器件包括：半导体本体; 形成在主体上的栅极绝缘膜; 以及形成在体内的源极/漏极区域和形成在栅极绝缘膜上的栅电极膜的MOS晶体管。栅极电极膜由具有不同蚀刻速率的两个或更多个膜组成。栅极蚀刻停止在复合膜的界面处以形成反T栅电极结构; 并且在组件膜之间观察到导电。因此，可以控制栅极和漏极之间的重叠。

2. 发明授权

US5371023A Gate circuit, semiconductor integrated circuit device and method of fabrication thereof, semiconductor memory and microprocessor 失效
标题翻译：门电路，半导体集成电路器件及其制造方法，半导体存储器和微处理器
公开(公告)号：US5371023A
公开(公告)日：1994-12-06
申请号：US895815
申请日：1992-06-09
申请人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
发明人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
IPC分类号： H01L27/06 , H01L27/105 , H01L21/20
CPC分类号： H01L27/105 , H01L27/0623
摘要： A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.
摘要翻译：公开了一种新颖的门电路。第一半导体开关包括连接在第一电位电平和输出节点之间的一对主端子，其中响应于具有第一逻辑电平和第二逻辑电平的输入信号而保持高阻抗状态，并且阻抗状态仅在输入信号从第一逻辑电平变化到第二逻辑电平的过渡期间从高变化为低电平。第二半导体开关包括插入在与第一电位电平不同的第二电位电平和输出节点之间的一对主端子，其中响应于输入信号保持高阻抗状态，并且阻抗状态从高变为仅在输入信号从第二逻辑电平变为第一逻辑电平的瞬态期间为低电平。

3. 发明授权

US4392158A Interlaced solid-state imaging device 失效
标题翻译：隔行固态成像装置
公开(公告)号：US4392158A
公开(公告)日：1983-07-05
申请号：US257461
申请日：1981-04-24
申请人： Masakazu Aoki , Haruhisa Ando , Shinya Ohba , Shoji Hanamura , Iwao Takemoto , Ryuichi Izawa
发明人： Masakazu Aoki , Haruhisa Ando , Shinya Ohba , Shoji Hanamura , Iwao Takemoto , Ryuichi Izawa
IPC分类号： H01L27/146 , H04N5/335 , H04N5/341 , H04N5/355 , H04N5/359 , H04N5/374 , H04N3/14
CPC分类号： H04N3/1512 , H01L27/14643
摘要： In a solid-state imaging device having a plurality of photodiodes which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements and a group of vertical switching elements which pick up the photodiodes, and a horizontal scanning circuit and a vertical scanning circuit which impress scanning pulses on the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism which picks up a plurality of vertical scanning lines by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows; a solid-state imaging device characterized in that said interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements.
摘要翻译：在具有在相同的半导体主体上二维排列的多个光电二极管的固态成像装置中，一组水平切换元件和一组拾取光电二极管的垂直开关元件，以及水平扫描电路和垂直扫描电路，其分别在水平和垂直开关元件上施加扫描脉冲，并且具有隔行扫描机构，其通过隔行扫描开关元件拾取多条垂直扫描线，以允许水平扫描多条扫描线的扫描线行一种固态成像装置，其特征在于，所述隔行扫描机构包括绝缘栅场效应晶体管，用于恢复由于交错开关元件而经历电压降的扫描脉冲的电压电平。

4. 发明授权

US4316205A Solid-state imaging device 失效
标题翻译：固态成像装置
公开(公告)号：US4316205A
公开(公告)日：1982-02-16
申请号：US119383
申请日：1980-02-07
申请人： Masakazu Aoki , Iwao Takemoto , Masaharu Kubo , Ryuichi Izawa
发明人： Masakazu Aoki , Iwao Takemoto , Masaharu Kubo , Ryuichi Izawa
IPC分类号： H01L27/146 , H01L31/113 , H04N5/335 , H04N5/374 , H01L27/14
CPC分类号： H01L31/1136 , H01L27/14643
摘要： In a solid-state imaging device having in one major surface region of a monolithic semiconductor body, photodiodes which are arrayed in two dimensions, vertical switching MOS transistors and horizontal switching MOS transistors which address the photodiodes, MOS transistors which constitute vertical and horizontal scanning circuits for turning "on" and "off" the switching MOS transistors, and MOS transistors which constitute other peripheral circuitry, the photodiodes being constructed of source regions of the vertical switching MOS transistors and the semiconductor body; a solid-state imaging device characterized in that among source and drain regions of the various MOS transistors, the source regions of the vertical switching MOS transistors are lower in the surface impurity concentration and deeper in the junction depth than the other source and drain regions.
摘要翻译：在具有单片半导体主体的一个主表面区域的固态成像装置中，以二维排列的光电二极管，构成光电二极管的垂直开关MOS晶体管和水平开关MOS晶体管，构成垂直和水平扫描电路的MOS晶体管为了使开关MOS晶体管“开”和“关”，构成其它外围电路的MOS晶体管，该光电二极管由垂直开关MOS晶体管和半导体本体的源极区构成; 一种固态成像装置，其特征在于，在各种MOS晶体管的源极和漏极区域中，垂直开关MOS晶体管的源极区域的表面杂质浓度较低，并且结深度比其他源极和漏极区域更深。

5. 发明授权

US4349743A Solid-state imaging device 失效
标题翻译：固态成像装置
公开(公告)号：US4349743A
公开(公告)日：1982-09-14
申请号：US206865
申请日：1980-11-14
申请人： Shinya Ohba , Shoji Hanamura , Toshifumi Ozaki , Masaharu Kubo , Masaaki Nakai , Kenji Takahashi , Masakazu Aoki , Iwao Takemoto , Haruhisa Ando , Ryuichi Izawa
发明人： Shinya Ohba , Shoji Hanamura , Toshifumi Ozaki , Masaharu Kubo , Masaaki Nakai , Kenji Takahashi , Masakazu Aoki , Iwao Takemoto , Haruhisa Ando , Ryuichi Izawa
IPC分类号： H01L27/14 , H01L27/146 , H04N3/14 , H04N5/335 , H04N5/341 , H04N5/359 , H04N5/365 , H04N5/372 , H04N5/374 , H04N5/378
CPC分类号： H01L27/14643 , H04N3/1512 , H04N3/1568
摘要： A solid-state imaging device wherein a MOS sensor is employed for a photosensor part, a CTD shift register is employed for a read-out circuit, first and second transfer gates are connected between vertical signal output lines and the CTD, and a reset gate is connected between a juncture of the first and second transfer gates and a reset voltage line. A method is adopted in which signal outputs of a plurality of rows are transferred to the CTD in a horizontal blanking period, and signals of a plurality of rows are simultaneously read out in a horizontal scanning period. At the signal transfer, bias charges are dumped into the vertical signal output lines from the CTD, and mixed charges consisting of the bias charges and signal charges are transferred to the CTD. Thereafter, the signals are read out.
摘要翻译：一种固态成像装置，其中MOS传感器用于光电传感器部分，CTD移位寄存器用于读出电路，第一和第二传输门连接在垂直信号输出线和CTD之间，复位门连接在第一和第二传输门的接合点与复位电压线之间。采用在水平消隐期间将多行的信号输出传送到CTD的方法，并且在水平扫描期间同时读出多行的信号。在信号传输中，偏置电荷从CTD倾倒到垂直信号输出线路中，由偏置电荷和信号电荷组成的混合电荷转移到CTD。此后，读出信号。

6. 发明授权

US4295055A Circuit for generating scanning pulses 失效
标题翻译：用于产生扫描脉冲的电路
公开(公告)号：US4295055A
公开(公告)日：1981-10-13
申请号：US46028
申请日：1979-06-06
申请人： Iwao Takemoto , Norio Koike , Shinya Ohba , Haruhisa Ando , Masaaki Nakai , Syoji Hanamura , Ryuichi Izawa , Masaharu Kubo , Masakazu Aoki , Shuhei Tanaka
发明人： Iwao Takemoto , Norio Koike , Shinya Ohba , Haruhisa Ando , Masaaki Nakai , Syoji Hanamura , Ryuichi Izawa , Masaharu Kubo , Masakazu Aoki , Shuhei Tanaka
IPC分类号： G11C19/00 , G11C19/18 , G11C19/28 , H01L27/146 , H01L31/10 , H03K5/15 , H04N3/14
CPC分类号： H03K5/15093 , G11C19/184 , G11C19/28
摘要： A circuit for generating scanning pulses comprising a plurality of stages of basic circuits connected in series, said each basic circuit comprising first, second and third insulated gate field-effect transistors (MISTs) each of which has first and second terminals each being either of source and drain terminals and a gate terminal, said first terminal of said first MIST being used as a clock pulse-applying terminal, said gate terminal of said first MIST being used as an input terminal, said second terminal of said first MIST and said first terminal and said gate terminal of said second MIST being connected and used as a scanning pulse output terminal, said second terminal of said second MIST and said first terminal of said third MIST being connected and used as an output terminal, said second terminal of said third MIST being used as a ground terminal, said gate terminal of said third MIST being used as a feedback input terminal.
摘要翻译：一种用于产生扫描脉冲的电路，包括串联连接的多级基本电路，所述每个基本电路包括第一，第二和第三绝缘栅极场效应晶体管（MIST），每个绝缘栅场效应晶体管的第一和第二端子均为源极所述第一MIST的所述第一端子用作时钟脉冲施加端子，所述第一MIST的所述栅极端子用作输入端子，所述第一MIST的所述第二端子和所述第一端子的所述第一端子并且所述第二MIST的所述栅极端子被连接并用作扫描脉冲输出端子，所述第二MIST的所述第二端子和所述第三MIST的所述第一端子被连接并用作输出端子，所述第三MIST的所述第二端子被用作接地端子，所述第三MIST的所述栅极端子用作反馈输入端子。

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