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1. 发明授权

US5371023A Gate circuit, semiconductor integrated circuit device and method of fabrication thereof, semiconductor memory and microprocessor 失效
标题翻译：门电路，半导体集成电路器件及其制造方法，半导体存储器和微处理器
公开(公告)号：US5371023A
公开(公告)日：1994-12-06
申请号：US895815
申请日：1992-06-09
申请人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
发明人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
IPC分类号： H01L27/06 , H01L27/105 , H01L21/20
CPC分类号： H01L27/105 , H01L27/0623
摘要： A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.
摘要翻译：公开了一种新颖的门电路。第一半导体开关包括连接在第一电位电平和输出节点之间的一对主端子，其中响应于具有第一逻辑电平和第二逻辑电平的输入信号而保持高阻抗状态，并且阻抗状态仅在输入信号从第一逻辑电平变化到第二逻辑电平的过渡期间从高变化为低电平。第二半导体开关包括插入在与第一电位电平不同的第二电位电平和输出节点之间的一对主端子，其中响应于输入信号保持高阻抗状态，并且阻抗状态从高变为仅在输入信号从第二逻辑电平变为第一逻辑电平的瞬态期间为低电平。

2. 发明授权

US5055904A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5055904A
公开(公告)日：1991-10-08
申请号：US495762
申请日：1990-03-19
申请人： Masataka Minami , Kazushige Sato , Atsuo Watanabe , Shoji Shukuri , Takashi Nishida , Takahiro Nagano
发明人： Masataka Minami , Kazushige Sato , Atsuo Watanabe , Shoji Shukuri , Takashi Nishida , Takahiro Nagano
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/11
CPC分类号： H01L27/0623 , H01L27/1112 , Y10S257/903
摘要： A semicondcutor device and a manufacturing method thereof are disclosed in which higher integration can be achieved without increasing the total manufacturing steps. The semiconductor device includes at least two MOS transistors having the same channel types, the gate electrodes of which are constructed of polycrystal silicon layers which contain an impurity, and a bipolar transistor, the base electrode of which is constructed of a polycrystal silicon layer which contains and impurity. In particular, the respective gate electrodes of the two MOS transistors contain impurities of different conductivity types from one another.
摘要翻译：公开了一种半切割器件及其制造方法，其中可以在不增加总制造步骤的情况下实现更高的集成度。半导体器件包括至少两个具有相同沟道类型的MOS晶体管，其栅电极由含有杂质的多晶硅层构成;以及双极晶体管，其基极由多晶硅层构成，该多晶硅层含有和杂质。特别地，两个MOS晶体管的各个栅电极彼此具有不同导电类型的杂质。

3. 发明授权

US4916500A MOS field effect transistor device with buried channel 失效
标题翻译： MOS场效应晶体管器件具有埋入通道
公开(公告)号：US4916500A
公开(公告)日：1990-04-10
申请号：US78987
申请日：1987-07-29
申请人： Yoshiaki Yazawa , Atsuo Watanabe , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano
发明人： Yoshiaki Yazawa , Atsuo Watanabe , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano
IPC分类号： H01L29/10 , H01L29/78 , H01L29/786 , H01L29/808
CPC分类号： H01L29/78696 , H01L29/105 , H01L29/78 , H01L29/7838 , H01L29/808
摘要： The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.
摘要翻译：本发明涉及一种包括第一导电类型或绝缘体的半导体衬底的半导体器件，包括设置在所述半导体衬底或所述绝缘体上的第二导电类型的杂质层的源极，包括第二导电类型或绝缘体的杂质层的漏极设置在所述半导体衬底或所述绝缘体上的导电类型，形成在所述源极和所述漏极之间的第一导电类型的杂质层，经由绝缘膜形成在所述第一导电类型的所述杂质层上的栅极和第二导电类型的杂质浓度低于所述源极和漏极的第二导电类型，所述第二导电类型的所述杂质层设置在所述源极，所述漏极和所述第一导电类型的所述杂质层之间，所述第一导电类型的所述半导体衬底导电类型或所述绝缘体。

4. 发明授权

US5726488A Semiconductor device having semiconductor elements formed in a retrograde well structure 失效
标题翻译：具有形成在逆行井结构中的半导体元件的半导体器件
公开(公告)号：US5726488A
公开(公告)日：1998-03-10
申请号：US243325
申请日：1994-05-16
申请人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
发明人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78 , H01L27/02
CPC分类号： H01L27/0623 , H01L21/8238 , H01L21/8249 , Y10S257/921
摘要： A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
摘要翻译：半导体器件具有在衬底的表面中形成的阱区，并且具有形成在阱区中的诸如MOSFET和双极晶体管的功能部分。阱区域的载流子浓度分布呈深谷方向的谷状，其最小点浓度小于5×10 15 cm -3，位于距离其表面1.6m以内的位置底物。优选地，最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度，更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。

5. 发明授权

US4963973A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4963973A
公开(公告)日：1990-10-16
申请号：US323212
申请日：1989-03-13
申请人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
发明人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0623 , H01L21/8238 , H01L21/8249 , Y10S257/921
摘要： A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
摘要翻译：半导体器件具有在衬底的表面中形成的阱区，并且在阱区中形成有诸如MOSFET和双极晶体管的半导体元件。阱区域的载流子浓度分布呈深谷方向的谷状，其最小点浓度小于5×10 15 cm -3，位于距离其表面1.6m以内的位置底物。优选地，最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度，更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。

6. 发明授权

US5506156A Method of fabricating bipolar transistor having high speed and MOS transistor having small size 失效
标题翻译：制造具有高速度的双极晶体管的方法和具有小尺寸的MOS晶体管
公开(公告)号：US5506156A
公开(公告)日：1996-04-09
申请号：US279087
申请日：1994-07-22
申请人： Atsuo Watanabe , Kazushige Sato , Takahiro Nagano , Shoji Shukuri , Takashi Nishida
发明人： Atsuo Watanabe , Kazushige Sato , Takahiro Nagano , Shoji Shukuri , Takashi Nishida
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/265
CPC分类号： H01L21/8249 , Y10S148/009
摘要： A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.
摘要翻译：半导体器件包括多个第一导电类型的半导体区域和第二导电类型的多个半导体区域。具有第二导电类型的沟道的AMOS晶体管形成在第一导电类型的半导体区域中，并且在第二导电类型的半导体区域中形成具有第一导电类型的沟道的双极晶体管和MOS晶体管。第一导电类型的半导体区域由半导体层构成，其中杂质浓度随着其表面的深度而减小，第一导电类型的第一掩埋层形成在半导体衬底中，并且杂质在厚度方向上的浓度分布具有单个峰值，并且形成在半导体层和第一掩埋层之间的第一导电类型的第二掩埋层，并且其中厚度方向上的杂质浓度分布具有单峰值。在外延生长处理和场氧化处理完成之后，通过离子注入法形成第一和第二掩埋层。

7. 发明授权

US5132758A Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US5132758A
公开(公告)日：1992-07-21
申请号：US308777
申请日：1989-02-09
申请人： Masataka Minami , Youkou Wakui , Takahiro Nagano
发明人： Masataka Minami , Youkou Wakui , Takahiro Nagano
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/2815 , H01L29/42376 , H01L29/435 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： In a MOSFET of an LDD structure, a side wall is made conductive and connected to a gate through a resistance thereby to cause hot carriers taken into the side wall to be discharged to a gate through the resistance, whereby a channel resistance is prevented from being increased by an effect of carriers accumulated in the side wall. As a result, a reliable MOSFET with a short channel can be provided which is not degraded even if it is used for a long time.

8. 再颁专利

USRE34158E Complementary semiconductor device 失效
公开(公告)号：USRE34158E
公开(公告)日：1993-01-12
申请号：US744514
申请日：1991-08-13
申请人： Atsuo Watanabe , Takahiro Nagano , Takahide Ikeda , Naohiro Momma , Ryuichi Saito
发明人： Atsuo Watanabe , Takahiro Nagano , Takahide Ikeda , Naohiro Momma , Ryuichi Saito
IPC分类号： H01L21/762 , H01L21/763 , H01L21/8238 , H01L27/06 , H01L27/092
CPC分类号： H01L27/0928 , H01L21/76224 , H01L21/763 , H01L21/823892 , H01L27/0623
摘要： A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.

9. 发明授权

US4862240A Complementary semiconductor device 失效
标题翻译：互补半导体器件
公开(公告)号：US4862240A
公开(公告)日：1989-08-29
申请号：US85260
申请日：1987-08-12
申请人： Atsuo Watanabe , Takahiro Nagano , Takahide Ikeda , Naohiro Momma , Ryuichi Saito
发明人： Atsuo Watanabe , Takahiro Nagano , Takahide Ikeda , Naohiro Momma , Ryuichi Saito
IPC分类号： H01L29/78 , H01L21/74 , H01L21/762 , H01L21/763 , H01L21/8238 , H01L27/06 , H01L27/092
CPC分类号： H01L21/76224 , H01L21/74 , H01L21/76205 , H01L21/763 , H01L21/823892 , H01L27/092 , H01L27/0623
摘要： A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the well from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.
摘要翻译：一种单片互补半导体器件，包括由从表面延伸到衬底区域的电介质隔离区隔开的n型和p型阱区。阱区域包括高度掺杂的掩埋区域，其位于阱区域的底部并且将阱中的有源区域与衬底区域分离。隔离区域比掩埋区域深。通过掩埋区域和深介电隔离区域的组合增强了井对阱隔离。包装密度和高速运转也可以提高。

10. 发明授权

US4948994A Semiconductor circuit for driving the base of a bipolar transistor 失效
标题翻译：用于驱动双极晶体管的基极的半导体电路
公开(公告)号：US4948994A
公开(公告)日：1990-08-14
申请号：US254568
申请日：1988-10-07
申请人： Takashi Akioka , Atsuo Watanabe , Takahiro Nagano
发明人： Takashi Akioka , Atsuo Watanabe , Takahiro Nagano
IPC分类号： H03K17/04 , H03K17/00 , H03K17/0412 , H03K17/567 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448 , H03K17/04126 , H03K2217/0036
摘要： A system providing a drive circuit for a bipolar transistor high in speed and low in power consumption even under a low source voltage using a MOSFET is disclosed. The base current of the bipolar transistor is supplied not by short-circuiting the collector and the base thereof by a MOSFET but from another base current source.

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