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1. 发明授权

US06300809B1 Double-edge-triggered flip-flop providing two data transitions per clock cycle 有权
标题翻译：双边沿触发器，每个时钟周期提供两个数据转换
公开(公告)号：US06300809B1
公开(公告)日：2001-10-09
申请号：US09616551
申请日：2000-07-14
申请人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
发明人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
IPC分类号： H03K312
CPC分类号： H03K3/012 , H03K3/037 , H03K3/0375
摘要： An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.
摘要翻译：一种包括用于提供时钟信号的时钟的装置，用于提供时钟信号的延迟版本的装置，具有由延迟的时钟信号的相反极性控制的时钟输入的两个透明锁存器，多路复用器具有（i）由锁存器和（ii）由时钟信号馈送的选择输入，以及用于提供用于选择时钟不活动的锁存器的选择信号的装置。优选地，每个锁存器具有扫描输入栅极和扫描输出栅极，并且第一锁存器的扫描输出被施加到第二锁存器的扫描输入以形成可扫描锁存器对。此外，优选地，该装置还包括用于将数据应用于第一和第二锁存器的数据端口和数据端口处的异或门，由此该装置产生门控时钟信号。还公开了一种操作该装置的方法。

2. 发明授权

US5920575A VLSI test circuit apparatus and method 失效
标题翻译： VLSI测试电路设备及方法
公开(公告)号：US5920575A
公开(公告)日：1999-07-06
申请号：US934326
申请日：1997-09-19
申请人： Roger Paul Gregor , Steven Frederick Oakland
发明人： Roger Paul Gregor , Steven Frederick Oakland
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318541
摘要： An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2. The inputs to the multiplexer are functional data D, scan data I, and the control is scan enable SE. The L1 master latch receives its input from the output of the multiplexer and is clocked by the NAND of a -FLUSH (-A CLOCK) with an +EdgeClock (-C CLOCK.) The L2 slave latch receives its data input from the output of the L1 master latch and is clocked with the AND of -FREEZE (B CLOCK) and +EdgeClock. The output of the flip flop is the output of the L2 slave latch. This flip flop structure supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.
摘要翻译： LSSD MUX D触发器包括多路复用器，主锁存器L1和从锁存器L2。多路复用器的输入是功能数据D，扫描数据I，控制是扫描使能SE。 L1主锁存器从多路复用器的输出端接收其输入，并由具有+ EdgeClock（-C CLOCK）的-FLUSH（-A CLOCK）的NAND提供时钟.L2从锁存器从其输出的输出端接收其数据输入 L1主机锁存器，并且与-FREEZE（B CLOCK）和+ EdgeClock的AND进行时钟控制。触发器的输出是L2从锁存器的输出。该触发器结构支持边缘敏感，电平敏感，功能，扫描，冻结，冲洗和测试操作。

3. 发明授权

US06222407B1 Dual mode programmable delay element 失效
标题翻译：双模式可编程延时元件
公开(公告)号：US06222407B1
公开(公告)日：2001-04-24
申请号：US09263035
申请日：1999-03-05
申请人： Roger Paul Gregor
发明人： Roger Paul Gregor
IPC分类号： H03H1126
CPC分类号： H03K5/131 , H03K5/133
摘要： Rapid set-up is achieved in a programmable delay element having identical pairs of positionally corresponding delay stages in parallel arrays. The pairs of delay elements include identical arrangements of circuit elements and are replicable in a step-and-repeat fashion to simplify delay element manufacture for any arbitrary maximum delay time to be provided. Delay stages of the delay element are comprised of multiplexers. Outputs of respective delay stages are simultaneously stored as a signal transition is propagated through the delay stages in a first order to program the delay element. Thereafter, signals are propagated through selected delay stages in a second order controlled by the simultaneously stored outputs of respective delay stages during the propagation of the signal transition. The selected stages through which a signal is propagated in the second order are the same stages through which the signal transition had propagated in the first order at the time the delay stage outputs were simultaneously stored.
摘要翻译：在具有并行阵列中具有相同位置对应的延迟级对的可编程延迟元件中实现快速设置。这些延迟元件对包括电路元件的相同布置，并且可以逐步重复的方式复制，以简化要提供的任意任意最大延迟时间的延迟元件制造。延迟元件的延迟级由多路复用器组成。各个延迟级的输出同时存储，因为信号转换通过延迟级以一级传播，以对延迟元件进行编程。此后，在信号转换的传播期间，信号以由相应的延迟级的同时存储的输出控制的二级传播通过选定的延迟级。信号以二级传播的选择级是在延迟级输出被同时存储时信号转换以一级传播的相同级。

4. 发明授权

US5760627A Low power CMOS latch 失效
标题翻译：低功耗CMOS锁存器
公开(公告)号：US5760627A
公开(公告)日：1998-06-02
申请号：US614123
申请日：1996-03-12
申请人： Roger Paul Gregor , Gary Francis Yenik
发明人： Roger Paul Gregor , Gary Francis Yenik
IPC分类号： H03K3/356
CPC分类号： H03K3/356147 , H03K3/356121
摘要： A latch comprises first and second NFETs and a first inverter. Data is applied without inversion to the gate of the first NFET and via the first inverter to the gate of the second NFET. A third NFET has a drain connected to the sources of the first and second NFETs. A clock is applied to the gate of the third NFET. Thus, there is only one NFET subject to the constant switching the clock, and therefore the constant power dissipation caused by the clock. To latch the data from the first and second NFETS, first and second inverters are connected in paralle with each other such that the output of each inverter is connected to the input of the other inverter. The input of one of the inverters is connected to the drain of the first NFET and the input of the other inverter is connected to the drain of the second NFET. A second stage of latching is also disclosed.
摘要翻译：锁存器包括第一和第二NFET和第一反相器。数据在没有反相的情况下施加到第一NFET的栅极并且经由第一反相器施加到第二NFET的栅极。第三NFET具有连接到第一和第二NFET的源极的漏极。时钟被施加到第三NFET的栅极。因此，只有一个NFET受时钟的恒定切换，因此由时钟引起的恒定功耗。为了锁存来自第一和第二NFET的数据，第一和第二反相器彼此并联连接，使得每个逆变器的输出连接到另一个反相器的输入端。其中一个反相器的输入连接到第一NFET的漏极，而另一个反相器的输入端连接到第二个NFET的漏极。还公开了锁定的第二阶段。

5. 发明授权

US5710742A High density two port SRAM cell for low voltage CMOS applications 失效
标题翻译：用于低电压CMOS应用的高密度双端口SRAM单元
公开(公告)号：US5710742A
公开(公告)日：1998-01-20
申请号：US440285
申请日：1995-05-12
申请人： Eric Lee Carter , Roger Paul Gregor , Moon Ho Lee , Michael Richard Ouellette
发明人： Eric Lee Carter , Roger Paul Gregor , Moon Ho Lee , Michael Richard Ouellette
IPC分类号： G11C8/16 , G11C11/412 , G11C11/00
CPC分类号： G11C8/16 , G11C11/412
摘要： A two-port memory cell design which permits simultaneous reading and writing of cells which are on the same wordline but on different Bit Select lines without increase in Read Access Time, and while maintaining memory functionality at low voltages. The memory cell uses a standard 6 transistor design to provide a differential read for fast access plus another three transistors are added to each cell to provide a means of differentially writing the cell and de-gating the write if the bit-select is not active. This cell design has applicability to multi-port memories as well.
摘要翻译：双端口存储单元设计允许同时读取和写入在同一字线上但不同位选择行上的单元，而不增加读取访问时间，同时在低电压下保持存储器功能。存储单元使用标准6晶体管设计来提供用于快速存取的差分读取，并且另外三个晶体管被添加到每个单元以提供差分写入单元的手段，并且如果位选择不活动则解除写入。该单元设计也适用于多端口存储器。

6. 发明授权

US06509725B1 Self-regulating voltage divider for series-stacked voltage rails 失效
标题翻译：用于串联堆叠电压轨的自调节分压器
公开(公告)号：US06509725B1
公开(公告)日：2003-01-21
申请号：US09683025
申请日：2001-11-09
申请人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
发明人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
IPC分类号： G05F304
CPC分类号： G06F1/26
摘要： A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.
摘要翻译：一种用于在多个串联电压平面之间实现自调节电压分配的系统和方法。本发明的系统结合在具有用于提供电流的源电源节点的源极电压平面和用于吸收从其提供的电流的源极接地节点。中间电压供应节点耦合在源电源电压节点和源极接地节点之间，用于将源极电压平面分成多个中间电压平面。本发明的自调节分压器包括第一电容器和第二电容器，每个可控制地耦合在源电源电压节点和中间电压供应节点之间，或者在中间电压供应节点和源极接地节点之间，使得在中间电压平面之间实现电压电平平衡。

7. 发明授权

US06421784B1 Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element 有权
标题翻译：具有精细延迟元件的可编程延迟电路有选择地接收粗延迟元件的输入信号和输出信号
公开(公告)号：US06421784B1
公开(公告)日：2002-07-16
申请号：US09263671
申请日：1999-03-05
申请人： Albert Manhee Chu , Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Roger Paul Gregor
发明人： Albert Manhee Chu , Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Roger Paul Gregor
IPC分类号： G06F112
CPC分类号： H03K5/131 , G06F5/06 , H03K2005/00058 , H03K2005/00195 , H03L7/0814 , H03L7/0818
摘要： A programmable delay element having a fine delay circuit with fractional units of delay. The fine delay circuit has a fine delay circuit with a plurality of selectable delay paths, each delay path having an associated delay interval. The fine delay element is electrically-coupled to a data terminal for receiving and delaying an input signal. A control circuit is electrically-coupled to the fine delay circuit to select the delay path for the input signal. In a further aspect of the invention, the fine delay circuit is electrically-coupled to a coarse delay circuit having a plurality of selectable delay blocks in a repetitive block configuration. The coarse delay circuit is electrically-coupled to a second data terminal for receiving and inserting a second signal through said fine delay circuit. The control circuit is electrically-coupled to the selective delay path of the fine delay circuit and the coarse delay circuit such that either a fine delay, a coarse delay, or a coarse and a fine delay can be selected.
摘要翻译：具有具有分数单位延迟的精细延迟电路的可编程延迟元件。精细延迟电路具有具有多个可选延迟路径的精细延迟电路，每个延迟路径具有相关联的延迟间隔。精细延迟元件电耦合到数据终端，用于接收和延迟输入信号。控制电路电耦合到精细延迟电路以选择输入信号的延迟路径。在本发明的另一方面，精细延迟电路电耦合到具有重复块配置中的多个可选延迟块的粗略延迟电路。粗延迟电路电耦合到第二数据终端，用于通过所述精细延迟电路接收和插入第二信号。控制电路电耦合到精细延迟电路和粗略延迟电路的选择延迟路径，使得可以选择精细延迟，粗略延迟或粗略和精细延迟。

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