专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

US20240267036A1 METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS 审中-公开
公开(公告)号：US20240267036A1
公开(公告)日：2024-08-08
申请号：US18615361
申请日：2024-03-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED
发明人： Huaixin XIAN , Qingchao MENG , Yang ZHOU , Shang-Chih HSIEH
IPC分类号： H03K3/037 , H01L27/105 , H01L29/02 , H01L29/06 , H01L29/10 , H01L29/417 , H03K3/288 , H03K3/289 , H03K3/356 , H03K3/3562
CPC分类号： H03K3/0372 , H01L27/105 , H01L29/02 , H01L29/06 , H01L29/1075 , H01L29/41725 , H03K3/288 , H03K3/289 , H03K3/356017 , H03K3/356104 , H03K3/356113 , H03K3/356147 , H03K3/3562 , H03K3/35625
摘要： An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure

2. 发明授权

US07622955B2 Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme 有权
标题翻译：功率节省与电平移位边界隔离触发器（LSIFF）和时钟控制的数据保留方案
公开(公告)号：US07622955B2
公开(公告)日：2009-11-24
申请号：US12104580
申请日：2008-04-17
申请人： Ramaprasath Vilangudipitchai , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
发明人： Ramaprasath Vilangudipitchai , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
IPC分类号： H03K19/094
CPC分类号： H03K3/356147 , H03K3/0375
摘要： An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.
摘要翻译：用于为具有数据保持的电路提供主动模式功率降低的装置包括用于锁存数据输入的主从触发器（MSFF）。耦合到MSFF的输出电平移位器（OLS）保留数据输入以响应MSFF在有功功率节省模式（APSM）中可操作以降低功率。在APSM中操作的OLS提供具有可配置电压的电平移位器输出，从而提供输出隔离。在主动模式和APSM之间的MSFF操作模式的改变与保留（RET）模式输入无关。

3. 发明授权

US07508247B2 Source drive circuit 有权
标题翻译：源驱动电路
公开(公告)号：US07508247B2
公开(公告)日：2009-03-24
申请号：US11469214
申请日：2006-08-31
申请人： Ching-Wu Tseng , Alex Tang
发明人： Ching-Wu Tseng , Alex Tang
IPC分类号： H03L5/00
CPC分类号： G09G3/3688 , G02F1/13306 , G09G2310/0289 , H03K3/356147
摘要： A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.
摘要翻译：提供可锁定电压电平转换器。可锁定电压电平移位器包括：电压电平移位器，接收原始输入信号，并根据第一相位控制信号的定时序列产生高电压信号; 以及耦合到电压电平移位器的高电压触发器，接收高电压信号和第二相位控制信号，高电平触发器根据第二相位控制信号的定时序列来锁存高电压信号;以及输出高压输出信号。可锁定电压电平转换器可用于源驱动电路，以减少布局面积和生产成本。

4. 发明授权

US07504871B2 Flip-flops and electronic digital circuits including the same 有权
标题翻译：触发器和包括其的电子数字电路
公开(公告)号：US07504871B2
公开(公告)日：2009-03-17
申请号：US11819388
申请日：2007-06-27
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K3/00
CPC分类号： H03K3/356121 , H03K3/356147 , H03K3/356191
摘要： A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.
摘要翻译：触发器包括接收时钟信号和第一信号的第一电路，并且当时钟信号进入有效电平时，将第一和第二输出信号转换到第一电平，第二电路将第一信号转换到第一电平在第一和第二输出信号进入第一级之后。当时钟信号处于有效电平并且第一信号处于第一电平时，第一电路将第一和第二输入信号从第一和第二输入端传送到第一和第二输出端。

5. 发明授权

US07373533B2 Programmable I/O cell capable of holding its state in power-down mode 有权
标题翻译：可编程I / O单元能够在掉电模式下保持其状态
公开(公告)号：US07373533B2
公开(公告)日：2008-05-13
申请号：US11241277
申请日：2005-09-30
申请人： Biranchinath Sahu , Douglas F. Pastorello , Golam R. Chowdhury
发明人： Biranchinath Sahu , Douglas F. Pastorello , Golam R. Chowdhury
IPC分类号： G06F1/26
CPC分类号： H03K3/0375 , H03K3/356147 , H03K19/0008
摘要： The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
摘要翻译：本发明包括一个微控制器单元，其包括用于产生掉电信号的处理器。控制逻辑响应于掉电信号产生保持信号。电压调节器响应于输入电压提供调节电压，并响应于掉电信号而断电。响应于稳压器进入断电状态，由调节电压供电的至少一个数字设备进入断电模式。所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。输入/输出单元也被连接以接收保持信号。当至少一个数字设备进入掉电状态时，输入/输出单元响应于保持信号维持数字输出信号的最后状态。

6. 发明申请

US20060244690A1 DATA LATCH CIRCUIT, DRIVING METHOD OF THE DATA LATCH CIRCUIT, AND DISPLAY DEVICE 有权
标题翻译：数据锁存电路，数据锁存电路的驱动方法和显示装置
公开(公告)号：US20060244690A1
公开(公告)日：2006-11-02
申请号：US11279630
申请日：2006-04-13
申请人： Mitsuaki OSAME , Tatsuro UENO
发明人： Mitsuaki OSAME , Tatsuro UENO
IPC分类号： G09G3/30
CPC分类号： G09G3/20 , G09G3/2022 , G09G3/3258 , G09G3/3266 , G09G3/3275 , G09G2300/0842 , G09G2300/0861 , G09G2310/027 , G09G2310/0294 , G09G2330/021 , H03K3/356147
摘要： The present invention provides a data latch circuit which can operate stably with a low-amplitude signal, which consumes less electric power, and which is resistant against the variation in TFTs. When an analog switch is turned on, a data signal is inputted to a gate electrode of an n-channel TFT and, at this time, VDD is supplied to an input terminal of an inverter. When the analog switch in turned off, the n-channel TFT is turned on or off depending on a level of the data signa. When the data signal is at an H level, the n-channel TFT is turned on and VSS is supplied to the input terminal of the inverter. When the data signal is at an L level, VDD is supplied to an input terminal of the inverter. Therefore, only VDD and VSS levels are applied to the input terminal of the inverter.
摘要翻译：本发明提供一种数据锁存电路，其能够以低幅度信号稳定地操作，其消耗较少的电力，并且能够抵抗TFT的变化。当模拟开关导通时，数据信号被输入到n沟道TFT的栅电极，此时，VDD被提供给逆变器的输入端。当模拟开关关闭时，n沟道TFT根据数据信号的电平开启或关闭。当数据信号为H电平时，n沟道TFT导通，VSS被提供给反相器的输入端。当数据信号为L电平时，VDD被提供给变频器的输入端子。因此，只有VDD和VSS电平施加到变频器的输入端。

7. 发明申请

US20060028243A1 Programmable level shifter for wide range operation purpose 有权
公开(公告)号：US20060028243A1
公开(公告)日：2006-02-09
申请号：US10912806
申请日：2004-08-06
申请人： Chih-Hung Wu , Meng-Jer Wey
发明人： Chih-Hung Wu , Meng-Jer Wey
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356147
摘要： A programmable level shifter. The programmable level shifter comprises a first P-type FET, a first N-type FET, a second P-type FET, a second N-type FET, an inverter, and a programmable device. The first P-type FET is coupled between a fist power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

8. 发明申请

US20060007216A1 Liquid crystal display apparatus having level conversion circuit 有权
公开(公告)号：US20060007216A1
公开(公告)日：2006-01-12
申请号：US11148260
申请日：2005-06-09
申请人： Hideo Sato , Yoshiro Mikami , Hiroshi Kageyama , Tatsuya Ohkubo
发明人： Hideo Sato , Yoshiro Mikami , Hiroshi Kageyama , Tatsuya Ohkubo
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G3/3611 , G09G3/3674 , G09G3/3685 , G09G2310/0289 , H03K3/356147 , H03K19/018521
摘要： A liquid crystal display apparatus having a level conversion circuit in which a high speed operation can be attained and also a small transistor capacity can be obtained is provided. In the liquid crystal display apparatus, a signal circuit for driving pixel elements of a display unit and a scanning circuit are provided. The level conversion circuit is constituted of a first and a second transistors 111 and 112 in which a respective gate electrodes is connected to a first bias voltage power supply, and a third and a fourth transistors 121 and 122 in which a respective gate electrodes is connected to a second bias voltage power supply and a respective source electrodes is connected to a power supply.

9. 发明申请

US20050122134A1 Level shifter and flat panel display 审中-公开
标题翻译：电平移位器和平板显示器
公开(公告)号：US20050122134A1
公开(公告)日：2005-06-09
申请号：US10997029
申请日：2004-11-22
申请人： Yong-Sung Park , Yang-Wan Kim
发明人： Yong-Sung Park , Yang-Wan Kim
IPC分类号： G11C19/00 , G09G3/36 , H03K3/356 , H03K19/0175
CPC分类号： H03K3/356113 , G09G3/3674 , G09G2310/0289 , H03K3/356147
摘要： A level shifter includes first, second, third, and fourth transistors. The first transistor is operable by an applied first input signal and is for supplying a second input signal to a first main electrode of a transistor. The second transistor is operable by an applied second input signal and is for supplying a first input signal to a first main electrode of a transistor. The third transistor has a first main electrode coupled to a second main electrode of the first transistor and is operable by a signal outputted by the second transistor. The fourth transistor has a first main electrode coupled to a second main electrode of the second transistor and is operable by a signal outputted by the first transistor.
摘要翻译：电平移位器包括第一，第二，第三和第四晶体管。第一晶体管可通过施加的第一输入信号操作，并用于将第二输入信号提供给晶体管的第一主电极。第二晶体管可通过施加的第二输入信号操作，并且用于将第一输入信号提供给晶体管的第一主电极。第三晶体管具有耦合到第一晶体管的第二主电极的第一主电极，并且可由第二晶体管输出的信号操作。第四晶体管具有耦合到第二晶体管的第二主电极的第一主电极，并且可由第一晶体管输出的信号操作。

10. 发明申请

US20050052214A1 Level shifter circuit 审中-公开
标题翻译：电平移位电路
公开(公告)号：US20050052214A1
公开(公告)日：2005-03-10
申请号：US10747240
申请日：2003-12-30
申请人： Akihiro Sushihara
发明人： Akihiro Sushihara
IPC分类号： H03K19/0185 , H03K3/356 , H03L5/00
CPC分类号： H03K3/356113 , H03K3/356147
摘要： A level shifter circuit which is small in delay in operating speed and also small in power consumption is provided. An NMOS transistor is connected to an input terminal at its source, to an output terminal at its drain, and to a 2V power supply line at its gate. A PMOS transistor is connected to a 3V power supply line at its source and to the output terminal at its drain. Another NMOS transistor is connected to a ground line at its source and to the output terminal at its drain. A control circuit made up of transistors supplies a voltage, which is inverse to the voltage of the input terminal, to the NMOS and PMOS transistors.
摘要翻译：提供了一种电平移动器电路，其操作速度延迟小并且功耗小。 NMOS晶体管在其源极处连接到输入端子，在其漏极处连接到输出端子，并在其栅极处连接到2V电源线。 PMOS晶体管在其源极处连接到3V电源线，并在其漏极处连接到输出端子。另一个NMOS晶体管在其源极处连接到接地线并连接到其漏极处的输出端子。由晶体管组成的控制电路向NMOS和PMOS晶体管提供与输入端的电压相反的电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式