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1. 发明授权

US5925143A Scan-bypass architecture without additional external latches 失效
标题翻译：扫描旁路架构，无需额外的外部锁存器
公开(公告)号：US5925143A
公开(公告)日：1999-07-20
申请号：US857974
申请日：1997-05-16
申请人： Pamela Sue Gillis , Ravi Kumar Kolagotla , Dennis A. Miller , Maria Noack , Steven Frederick Oakland , Chris Joseph Rebeor , Thomas Gregory Sopchak , Jeanne Trinko-Mechler
发明人： Pamela Sue Gillis , Ravi Kumar Kolagotla , Dennis A. Miller , Maria Noack , Steven Frederick Oakland , Chris Joseph Rebeor , Thomas Gregory Sopchak , Jeanne Trinko-Mechler
IPC分类号： G01R31/3185 , G11C29/32 , G01R31/28
CPC分类号： G01R31/318586 , G01R31/318558 , G11C29/32
摘要： A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.
摘要翻译：用于测试包含可扫描存储器设备（诸如寄存器阵列）的集成电路芯片的扫描架构可在旁路模式中操作，在该旁路模式期间，每个器件或阵列中只有一小部分存储器单元插入到扫描路径中以基本上减少扫描路径电路芯片中其他逻辑元件测试期间的长度，测试时间和测试数据量。采用附加解码器逻辑在扫描旁路模式期间在器件或阵列中选择少量字，并且多路复用器电路从扫描路径中去除旁路字。通过将少量的寄存器阵列字留在扫描路径中，在旁路模式期间保留阵列上游逻辑的可观察性和阵列下游逻辑的可控性，而不需要额外的移位寄存器锁存器和其他外部逻辑组件。

2. 发明授权

US06300809B1 Double-edge-triggered flip-flop providing two data transitions per clock cycle 有权
标题翻译：双边沿触发器，每个时钟周期提供两个数据转换
公开(公告)号：US06300809B1
公开(公告)日：2001-10-09
申请号：US09616551
申请日：2000-07-14
申请人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
发明人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
IPC分类号： H03K312
CPC分类号： H03K3/012 , H03K3/037 , H03K3/0375
摘要： An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.
摘要翻译：一种包括用于提供时钟信号的时钟的装置，用于提供时钟信号的延迟版本的装置，具有由延迟的时钟信号的相反极性控制的时钟输入的两个透明锁存器，多路复用器具有（i）由锁存器和（ii）由时钟信号馈送的选择输入，以及用于提供用于选择时钟不活动的锁存器的选择信号的装置。优选地，每个锁存器具有扫描输入栅极和扫描输出栅极，并且第一锁存器的扫描输出被施加到第二锁存器的扫描输入以形成可扫描锁存器对。此外，优选地，该装置还包括用于将数据应用于第一和第二锁存器的数据端口和数据端口处的异或门，由此该装置产生门控时钟信号。还公开了一种操作该装置的方法。

3. 发明授权

US5920575A VLSI test circuit apparatus and method 失效
标题翻译： VLSI测试电路设备及方法
公开(公告)号：US5920575A
公开(公告)日：1999-07-06
申请号：US934326
申请日：1997-09-19
申请人： Roger Paul Gregor , Steven Frederick Oakland
发明人： Roger Paul Gregor , Steven Frederick Oakland
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318541
摘要： An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2. The inputs to the multiplexer are functional data D, scan data I, and the control is scan enable SE. The L1 master latch receives its input from the output of the multiplexer and is clocked by the NAND of a -FLUSH (-A CLOCK) with an +EdgeClock (-C CLOCK.) The L2 slave latch receives its data input from the output of the L1 master latch and is clocked with the AND of -FREEZE (B CLOCK) and +EdgeClock. The output of the flip flop is the output of the L2 slave latch. This flip flop structure supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.
摘要翻译： LSSD MUX D触发器包括多路复用器，主锁存器L1和从锁存器L2。多路复用器的输入是功能数据D，扫描数据I，控制是扫描使能SE。 L1主锁存器从多路复用器的输出端接收其输入，并由具有+ EdgeClock（-C CLOCK）的-FLUSH（-A CLOCK）的NAND提供时钟.L2从锁存器从其输出的输出端接收其数据输入 L1主机锁存器，并且与-FREEZE（B CLOCK）和+ EdgeClock的AND进行时钟控制。触发器的输出是L2从锁存器的输出。该触发器结构支持边缘敏感，电平敏感，功能，扫描，冻结，冲洗和测试操作。

4. 发明授权

US06567943B1 D flip-flop structure with flush path for high-speed boundary scan applications 有权
标题翻译： D触发器结构，具有高速边界扫描应用的齐平路径
公开(公告)号：US06567943B1
公开(公告)日：2003-05-20
申请号：US09545369
申请日：2000-04-07
申请人： Carl Frederick Barnhart , David Lackey , Steven Frederick Oakland
发明人： Carl Frederick Barnhart , David Lackey , Steven Frederick Oakland
IPC分类号： G01R3128
CPC分类号： G01R31/318541
摘要： A boundary scan cell includes a shift latch, an update latch and a flushable latch that each have at least a respective data input and at least a respective data output. The data output of the shift latch is coupled to the data input of the update latch. The boundary scan cell further includes control circuitry that controls operation of the flushable latch circuit. The control circuitry selects, as input data for the flushable latch, one of a functional logic signal and a boundary scan signal in response to a mode signal. If the mode signal indicates a test mode, the control circuitry selects the boundary scan signal as the input data and causes the flushable latch to flush through the input data to the data output of the flushable latch independent of a system clock signal. The boundary scan cell can be implemented as either an input or output cell and preferably is compliant with IEEE Std 1149.1.
摘要翻译：边界扫描单元包括移位锁存器，更新锁存器和可刷新锁存器，每个锁存器至少具有相应的数据输入和至少相应的数据输出。移位锁存器的数据输出耦合到更新锁存器的数据输入端。边界扫描单元还包括控制可冲洗锁存电路的操作的控制电路。控制电路响应于模式信号，选择功能逻辑信号和边界扫描信号之一作为可冲洗锁存器的输入数据。如果模式信号指示测试模式，则控制电路选择边界扫描信号作为输入数据，并且使得可冲洗的锁存器独立于系统时钟信号将输入数据刷新到可冲洗锁存器的数据输出。边界扫描单元可以被实现为输入或输出单元，并且优选地符合IEEE标准1149.1。

5. 发明授权

US5719879A Scan-bypass architecture without additional external latches 失效
公开(公告)号：US5719879A
公开(公告)日：1998-02-17
申请号：US577676
申请日：1995-12-21
申请人： Pamela Sue Gillis , Ravi Kumar Kolagotla , Dennis A. Miller , Maria Noack , Steven Frederick Oakland , Chris Joseph Rebeor , Thomas Gregory Sopchak , Jeanne Trinko-Mechler
发明人： Pamela Sue Gillis , Ravi Kumar Kolagotla , Dennis A. Miller , Maria Noack , Steven Frederick Oakland , Chris Joseph Rebeor , Thomas Gregory Sopchak , Jeanne Trinko-Mechler
IPC分类号： G01R31/3185 , G11C29/32 , G01R31/28
CPC分类号： G01R31/318586 , G01R31/318558 , G11C29/32
摘要： A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.

6. 发明授权

US06577156B2 Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox 有权
公开(公告)号：US06577156B2
公开(公告)日：2003-06-10
申请号：US09731147
申请日：2000-12-05
申请人： Darren L. Anand , John Edward Barth, Jr. , John Atkinson Fifield , Pamela Sue Gillis , Peter O. Jakobsen , Douglas Wayne Kemerer , David E. Lackey , Steven Frederick Oakland , Michael Richard Ouellette , William Robert Tonti
发明人： Darren L. Anand , John Edward Barth, Jr. , John Atkinson Fifield , Pamela Sue Gillis , Peter O. Jakobsen , Douglas Wayne Kemerer , David E. Lackey , Steven Frederick Oakland , Michael Richard Ouellette , William Robert Tonti
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/802
摘要： A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

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