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1. 发明授权

US08719516B2 Memory having internal processors and methods of controlling memory access 有权
标题翻译：具有内部处理器的内存和控制内存访问的方法
公开(公告)号：US08719516B2
公开(公告)日：2014-05-06
申请号：US12603393
申请日：2009-10-21
申请人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
发明人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.
摘要翻译：提供具有内部处理器的记忆和在这种存储器内的数据通信方法。一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。提取单元可以基于银行的可用性来执行命令。在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器等待存储体可用。

2. 发明申请

US20110093662A1 MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY 有权
标题翻译：具有内部处理器的内存和内存中的数据通信方法
公开(公告)号：US20110093662A1
公开(公告)日：2011-04-21
申请号：US12603376
申请日：2009-10-21
申请人： Robert M. Walker , Dan Skinner , Todd A. Merritt , J. Thomas Pawlowski
发明人： Robert M. Walker , Dan Skinner , Todd A. Merritt , J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F3/0613 , G06F3/0625 , G06F3/0659 , G06F3/067 , G06F3/0683 , G06F9/3001 , G06F9/30043 , G06F12/0813 , G06F13/4068 , G06F15/7821
摘要： Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).
摘要翻译：提供具有内部处理器的存储器，以及在这种存储器内的数据通信方法。在一个实施例中，内部处理器可以经由一个或多个缓冲器同时访问存储器设备上的存储器阵列上的一个或多个存储体。内部处理器可以耦合到能够访问多于一个存储体的缓冲器，或者耦合到多个缓冲器，每个缓冲器可以访问存储体，从而可以同时从不同的存储体中检索数据并存储在其中。此外，存储器设备可以被配置为通过存储器组件（诸如耦合到每个内部处理器的缓冲器）之间的耦合来在一个或多个内部处理器之间进行通信。因此，可以由不同的内部处理器执行多操作指令，并且可以将来自一个内部处理器的数据（例如中间结果）传送到存储器的另一内部处理器，从而能够并行执行指令。

3. 发明申请

US20110093665A1 MEMORY HAVING INTERNAL PROCESSORS AND METHODS OF CONTROLLING MEMORY ACCESS 有权
标题翻译：具有内部处理器的内存和控制存储器访问的方法
公开(公告)号：US20110093665A1
公开(公告)日：2011-04-21
申请号：US12603393
申请日：2009-10-21
申请人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
发明人： Robert M. Walker , Dan Skinner , J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.
摘要翻译：提供具有内部处理器的记忆和在这种存储器内的数据通信方法。一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。提取单元可以基于银行的可用性来执行命令。在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器来等待存储体可用。

4. 发明授权

US09477636B2 Memory having internal processors and data communication methods in memory 有权
标题翻译：存储器内存有内部处理器和数据通讯方式
公开(公告)号：US09477636B2
公开(公告)日：2016-10-25
申请号：US12603376
申请日：2009-10-21
申请人： Robert M. Walker , Dan Skinner , Todd A. Merritt , J. Thomas Pawlowski
发明人： Robert M. Walker , Dan Skinner , Todd A. Merritt , J. Thomas Pawlowski
IPC分类号： G06F12/00 , G06F15/78 , G06F12/08 , G06F3/06
CPC分类号： G06F13/1673 , G06F3/0613 , G06F3/0625 , G06F3/0659 , G06F3/067 , G06F3/0683 , G06F9/3001 , G06F9/30043 , G06F12/0813 , G06F13/4068 , G06F15/7821
摘要： Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).
摘要翻译：提供具有内部处理器的存储器，以及在这种存储器内的数据通信方法。在一个实施例中，内部处理器可以经由一个或多个缓冲器同时访问存储器设备上的存储器阵列上的一个或多个存储体。内部处理器可以耦合到能够访问多于一个存储体的缓冲器，或者耦合到多个缓冲器，每个缓冲器可以访问存储体，从而可以同时从不同的存储体中检索数据并存储在其中。此外，存储器设备可以被配置为通过存储器组件（诸如耦合到每个内部处理器的缓冲器）之间的耦合来在一个或多个内部处理器之间进行通信。因此，可以由不同的内部处理器执行多操作指令，并且可以将来自一个内部处理器的数据（例如中间结果）传送到存储器的另一内部处理器，从而能够并行执行指令。

5. 发明授权

US08769213B2 Multi-port memory and operation 有权
标题翻译：多端口内存和操作
公开(公告)号：US08769213B2
公开(公告)日：2014-07-01
申请号：US12546258
申请日：2009-08-24
申请人： Dan Skinner , J. Thomas Pawlowski
发明人： Dan Skinner , J. Thomas Pawlowski
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/1631 , G06F13/16 , G06F13/1636 , G11C7/1075 , G11C8/16 , Y02D10/14
摘要： Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.
摘要翻译：具有用于在端口之间传递命令的附加控制总线的多端口存储器具有可被配置为响应从外部控制总线接收的命令或从附加控制总线接收的命令的各个端口。这有助于端口的各种组合来改变存储器的带宽或延迟，以便于针对不同的应用定制性能特征。

6. 发明申请

US20110047311A1 MULTI-PORT MEMORY AND OPERATION 有权
标题翻译：多端口存储器和操作
公开(公告)号：US20110047311A1
公开(公告)日：2011-02-24
申请号：US12546258
申请日：2009-08-24
申请人： Dan Skinner , J. Thomas Pawlowski
发明人： Dan Skinner , J. Thomas Pawlowski
IPC分类号： G06F13/36
CPC分类号： G06F13/1631 , G06F13/16 , G06F13/1636 , G11C7/1075 , G11C8/16 , Y02D10/14
摘要： Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.
摘要翻译：具有用于在端口之间传递命令的附加控制总线的多端口存储器具有可被配置为响应从外部控制总线接收的命令或从附加控制总线接收的命令的各个端口。这有助于端口的各种组合来改变存储器的带宽或延迟，以便于针对不同的应用定制性能特征。

7. 发明授权

US09389833B2 Method and system to dynamically power-down a block of a pattern-recognition processor 有权
标题翻译：动态关闭模式识别处理器的块的方法和系统
公开(公告)号：US09389833B2
公开(公告)日：2016-07-12
申请号：US13538714
申请日：2012-06-29
申请人： J. Thomas Pawlowski
发明人： J. Thomas Pawlowski
IPC分类号： G06F1/32 , G06F7/02
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3206 , G06F7/02 , G06F2207/025 , G06N5/047
摘要： A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block.
摘要翻译：一种设备包括模式识别处理器。模式识别处理器包括块，使得每个块包括被配置成分析待分析的数据的至少一部分的多个特征单元并且选择性地提供分析的结果。模式识别处理器还包括被配置为动态地关闭该块的块去激活逻辑。

8. 发明授权

US08413007B2 Memory system and method using ECC with flag bit to identify modified data 有权
标题翻译：使用带有标志位的ECC的存储器系统和方法来识别修改的数据
公开(公告)号：US08413007B2
公开(公告)日：2013-04-02
申请号：US13026833
申请日：2011-02-14
申请人： J. Thomas Pawlowski , John Schreck
发明人： J. Thomas Pawlowski , John Schreck
IPC分类号： H03M13/00
CPC分类号： H03M13/151 , G06F11/10 , G06F11/1044 , G11C7/1006 , G11C11/406 , G11C29/44 , G11C29/52 , G11C2029/0411 , G11C2211/4062
摘要： A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.
摘要翻译： DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

9. 发明授权

US08359517B2 Memory system and method using partial ECC to achieve low power refresh and fast access to data 有权
标题翻译：使用部分ECC的内存系统和方法实现低功耗刷新和快速访问数据
公开(公告)号：US08359517B2
公开(公告)日：2013-01-22
申请号：US13026030
申请日：2011-02-11
申请人： J. Thomas Pawlowski
发明人： J. Thomas Pawlowski
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1076 , G06F11/1008 , G06F11/1044 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C29/52 , G11C2029/0411 , G11C2211/4062 , G11C2211/4067
摘要： A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.
摘要翻译： DRAM存储器件包括几组存储器单元，每个存储单元被分成第一组和第二组存储器单元。可以以相对较慢的速率刷新第一组中的存储器单元以减少DRAM器件消耗的功率。 DRAM设备中的错误检查和校正电路校正由相对较慢的刷新率引起的第一组存储器单元中的任何数据保留错误。第二组中的存储单元以正常速率刷新，速度足够快，不会发生数据保留错误。可以对DRAM装置中的模式寄存器进行编程，以选择第二组存储器单元的大小。

10. 发明授权

US08281395B2 Pattern-recognition processor with matching-data reporting module 有权
标题翻译：具有匹配数据报告模块的模式识别处理器
公开(公告)号：US08281395B2
公开(公告)日：2012-10-02
申请号：US12350132
申请日：2009-01-07
申请人： J. Thomas Pawlowski
发明人： J. Thomas Pawlowski
IPC分类号： H04L29/06 , G06F11/00 , G06F15/173 , G06F7/02 , G06F13/40
CPC分类号： G06N5/025 , G06F7/02 , G06F2207/025 , G06K9/62
摘要： Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a matching-data reporting module, which may have a buffer and a match event table. The buffer may be coupled to a data stream and configured to store at least part of the data stream, and the match event table may be configured to store data indicative of a buffer location corresponding with a start of a search criterion being satisfied.
摘要翻译：公开了方法和装置，其中包括模式识别处理器的装置。模式识别处理器可以包括匹配数据报告模块，其可以具有缓冲器和匹配事件表。缓冲器可以耦合到数据流并且被配置为存储数据流的至少一部分，并且匹配事件表可以被配置为存储指示与满足搜索条件的开始相对应的缓冲器位置的数据。

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